projects
/
libresoc-litex.git
/ history
commit
grep
author
committer
pickaxe
?
search:
re
summary
|
shortlog
|
log
|
commit
|
commitdiff
|
tree
first ⋅ prev ⋅ next
update README
[libresoc-litex.git]
/ ls180soc.py
2021-06-10
Luke Kenneth Casso...
whoops spimaster (mspi0) not connected up
commit
|
commitdiff
2021-06-09
Luke Kenneth Casso...
sort out PLL connection, in and out of peripheral inter...
commit
|
commitdiff
2021-06-09
Luke Kenneth Casso...
try setting domain to "CPU"
commit
|
commitdiff
2021-06-09
Luke Kenneth Casso...
try setting actual clk to pllclk_o
commit
|
commitdiff
2021-06-09
Luke Kenneth Casso...
add PLL clock loop-back into CPU
commit
|
commitdiff
2021-05-22
Luke Kenneth Casso...
match up PLL names
commit
|
commitdiff
2021-04-18
Luke Kenneth Casso...
rename PLL pins to match LIP6.fr PLL
commit
|
commitdiff
2021-04-18
Luke Kenneth Casso...
rename XICS memmap regions
commit
|
commitdiff
2021-04-18
Luke Kenneth Casso...
update to build ls180 4k SRAMs
commit
|
commitdiff
2021-04-05
Luke Kenneth Casso...
sort out sdr and sdmmc OE pad drive, no longer one...
commit
|
commitdiff
2021-04-01
Luke Kenneth Casso...
disable PLL for litex build, new variant
commit
|
commitdiff
2021-03-29
Luke Kenneth Casso...
must not add bus width parameter
commit
|
commitdiff
2021-03-28
Luke Kenneth Casso...
fix issues with port direction on several pads
commit
|
commitdiff
2021-03-27
Luke Kenneth Casso...
latest fighting with litex to get pad directions connec...
commit
|
commitdiff
2021-03-25
Luke Kenneth Casso...
debugging ls180 litex hell
commit
|
commitdiff
2021-03-22
Luke Kenneth Casso...
SDR pad mask output for DM
commit
|
commitdiff
2021-03-12
Luke Kenneth Casso...
splitting out litex files from soc repo into separate...
commit
|
commitdiff