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kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git]
/
manual
/
CHAPTER_CellLib.tex
2014-09-08
Clifford Wolf
Added $lcu cell type
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2014-09-04
Clifford Wolf
Removed $bu0 cell type
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2014-08-30
Clifford Wolf
Added $alu cell type
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2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
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2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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2014-08-15
Clifford Wolf
Removed old doc references to $safe_pmux
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2014-07-16
Clifford Wolf
Merged new $mem/$memwr WR_EN interface
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2014-07-16
Clifford Wolf
Changed the $mem/$memwr WR_EN input to a per-data-bit...
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2014-02-07
Clifford Wolf
Added $slice and $concat cell types
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2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-19
Clifford Wolf
Added $assert cell
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-02
Clifford Wolf
Added correct handling of $memwr priority
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2013-12-28
Clifford Wolf
Added new cell types to manual
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2013-09-15
Clifford Wolf
Moved common techlib files to techlibs/common
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2013-07-20
Clifford Wolf
Added Yosys Manual
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