kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git] / manual / CHAPTER_CellLib.tex
2014-09-08 Clifford WolfAdded $lcu cell type
2014-09-04 Clifford WolfRemoved $bu0 cell type
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-15 Clifford WolfRemoved old doc references to $safe_pmux
2014-07-16 Clifford WolfMerged new $mem/$memwr WR_EN interface
2014-07-16 Clifford WolfChanged the $mem/$memwr WR_EN input to a per-data-bit...
2014-02-07 Clifford WolfAdded $slice and $concat cell types
2014-02-03 Clifford WolfAdded TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
2014-01-20 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-19 Clifford WolfAdded $assert cell
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-02 Clifford WolfAdded correct handling of $memwr priority
2013-12-28 Clifford WolfAdded new cell types to manual
2013-09-15 Clifford WolfMoved common techlib files to techlibs/common
2013-07-20 Clifford WolfAdded Yosys Manual