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Merge branch 'xaig' into xc7mux
[yosys.git]
/
manual
/
CHAPTER_CellLib.tex
2019-05-31
Eddie Hung
Merge branch 'xaig' into xc7mux
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2019-05-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7mux
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2019-05-21
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-05-08
Clifford Wolf
Merge pull request #991 from kristofferkoch/gcc9-warnings
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2019-05-06
Clifford Wolf
Merge pull request #946 from YosysHQ/clifford/specify
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2019-05-06
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2019-05-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into cliff...
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2019-04-23
Clifford Wolf
Add $specrule cells for $setup/$hold/$skew specify...
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2019-04-23
Clifford Wolf
Add CellTypes support for $specify2 and $specify3
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-01-15
Clifford Wolf
Merge pull request #788 from whitequark/master
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2019-01-14
whitequark
manual: document some gates.
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2019-01-14
whitequark
manual: explain $tribuf cell.
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2019-01-07
Clifford Wolf
Fix typo in manual
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2018-12-31
Clifford Wolf
Merge pull request #766 from Icenowy/anlogic-latches
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2018-12-23
Clifford Wolf
Merge pull request #761 from whitequark/proc_clean_partial
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2018-12-23
Clifford Wolf
Merge branch 'master' of github.com:YosysHQ/yosys
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2018-12-22
Clifford Wolf
Merge pull request #757 from whitequark/manual_mem
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2018-12-21
whitequark
manual: make description of $meminit ports match reality.
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2018-12-20
whitequark
manual: fix typos.
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2018-12-20
whitequark
manual: document $meminit cell and memory_* passes.
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2018-02-23
Clifford Wolf
Merge branch 'forall'
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2018-02-23
Clifford Wolf
Add $allconst and $allseq cell types
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2017-05-17
Clifford Wolf
Add $_ANDNOT_ and $_ORNOT_ gates
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2017-02-25
Clifford Wolf
Merge branch 'master' of https://github.com/klammerj...
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2017-02-25
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2017-02-25
Clifford Wolf
Add $live and $fair cell types, add support for s_event...
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2017-02-11
Clifford Wolf
Merge branch 'master' of https://github.com/stv0g/yosys...
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2017-02-09
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2017-02-04
Clifford Wolf
Add $cover cell type and SVA cover() support
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2016-10-14
Clifford Wolf
Added $anyseq cell type
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2016-10-11
Clifford Wolf
Added $ff and $_FF_ cell types
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2016-08-30
Clifford Wolf
Removed $aconst cell type
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2016-08-28
Clifford Wolf
Removed $predict again
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2016-07-30
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2016-07-27
Clifford Wolf
Added $anyconst and $aconst
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2016-07-21
Clifford Wolf
Added $initstate cell type and vlog function
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2016-07-21
Clifford Wolf
After reading the SV spec, using non-standard predict...
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2016-07-13
Clifford Wolf
Added basic support for $expect cells
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-06-17
Clifford Wolf
Added $sop cell type and "abc -sop"
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2015-12-07
Clifford Wolf
Merge pull request #108 from cseed/master
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2015-09-25
Clifford Wolf
Added read-enable to memory model
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-26
Clifford Wolf
Added $assume cell type
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2015-01-19
Clifford Wolf
Added $equiv cell type
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2014-12-08
Clifford Wolf
Added more documentation fixmes for nontrivial register...
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-08
Clifford Wolf
Added $lcu cell type
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2014-09-04
Clifford Wolf
Removed $bu0 cell type
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2014-08-30
Clifford Wolf
Added $alu cell type
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2014-08-16
Clifford Wolf
Added additional gate types: $_NAND_ $_NOR_ $_XNOR_...
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2014-08-15
Clifford Wolf
Renamed $_INV_ cell type to $_NOT_
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2014-08-15
Clifford Wolf
Removed old doc references to $safe_pmux
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2014-07-16
Clifford Wolf
Merged new $mem/$memwr WR_EN interface
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2014-07-16
Clifford Wolf
Changed the $mem/$memwr WR_EN input to a per-data-bit...
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2014-02-07
Clifford Wolf
Added $slice and $concat cell types
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2014-02-03
Clifford Wolf
Added TRANSPARENT parameter to $memrd (and RD_TRANSPARE...
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2014-01-20
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-19
Clifford Wolf
Added $assert cell
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-02
Clifford Wolf
Added correct handling of $memwr priority
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2013-12-28
Clifford Wolf
Added new cell types to manual
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2013-09-15
Clifford Wolf
Moved common techlib files to techlibs/common
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2013-07-20
Clifford Wolf
Added Yosys Manual
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