kernel: TimingInfo to clamp -ve setup/edge-sensitive delays to zero
[yosys.git] / manual / PRESENTATION_Prog /
2020-01-29 Claire WolfMerge branch 'vector_fix' of https://github.com/Kmanfi...
2019-09-27 Aman GoelMerge pull request #7 from YosysHQ/master
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-12-04 Clifford WolfAdded some missing .gitignore in manual/
2014-11-08 Clifford WolfVarious documentation updates
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-06-22 Clifford WolfProgress in presentation