Merge branch 'master' into pr_reg_wire_error
[yosys.git] / manual /
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2018-02-23 Clifford WolfMerge branch 'forall'
2018-02-23 Clifford WolfAdd $allconst and $allseq cell types
2017-05-17 Clifford WolfAdd $_ANDNOT_ and $_ORNOT_ gates
2017-02-25 Clifford WolfMerge branch 'master' of https://github.com/klammerj...
2017-02-25 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2017-02-25 Clifford WolfAdd $live and $fair cell types, add support for s_event...
2017-02-11 Clifford WolfMerge branch 'master' of https://github.com/stv0g/yosys...
2017-02-09 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2017-02-05 Clifford WolfMerge pull request #304 from esden/gsed-darwin
2017-02-05 Piotr Esden-TempskiUse -E sed parameter instead of -r.
2017-02-04 Clifford WolfAdd $cover cell type and SVA cover() support
2016-11-02 Clifford WolfUpdated command reference in manual
2016-10-14 Clifford WolfAdded $anyseq cell type
2016-10-11 Clifford WolfAdded $ff and $_FF_ cell types
2016-08-30 Clifford WolfRemoved $aconst cell type
2016-08-28 Clifford WolfRemoved $predict again
2016-07-30 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-07-27 Clifford WolfAdded $anyconst and $aconst
2016-07-21 Clifford WolfAdded $initstate cell type and vlog function
2016-07-21 Clifford WolfAfter reading the SV spec, using non-standard predict...
2016-07-13 Clifford WolfAdded basic support for $expect cells
2016-07-08 Clifford WolfAdded warning about adding fsm_encoding attributes...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2016-06-17 Clifford WolfAdded $sop cell type and "abc -sop"
2016-05-14 Clifford WolfMinor presentation fixes
2016-04-23 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-04-21 Clifford WolfAdded "yosys -D" feature
2016-04-03 Clifford WolfMerge pull request #145 from laanwj/master
2016-04-03 Wladimir J. van... Fix a few typos in the manual
2016-04-01 Andrew ZonenbergMerge https://github.com/cliffordwolf/yosys
2016-03-31 Clifford WolfRenamed opt_share to opt_merge
2016-03-31 Clifford WolfRenamed opt_const to opt_expr
2016-03-07 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2016-02-29 Clifford WolfMerge pull request #119 from SebKuzminsky/spelling...
2016-02-28 Sebastian Kuzminskyuser-facing spelling fixes
2016-02-14 Clifford WolfUpdated command reference in manual
2015-12-15 Clifford WolfMerge pull request #110 from scanlime/master
2015-12-15 Micah Elizabeth... Remove nonportable "-r" option from xargs
2015-12-07 Clifford WolfMerge pull request #108 from cseed/master
2015-09-25 Clifford WolfAdded read-enable to memory model
2015-08-14 Larry DoolittleAnother block of spelling fixes
2015-08-14 Clifford WolfRe-created command-reference-manual.tex, copied some...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-08-13 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-08-13 Clifford WolfMore ASCII encoding fixes
2015-08-13 Clifford WolfFixed CRLF line endings
2015-08-13 Clifford WolfSome ASCII encoding fixes (comments and docs) by Larry...
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-04-04 Clifford Wolfappnote 012 fix
2015-04-04 Clifford WolfAppnote 012
2015-04-04 Clifford WolfMerge pull request #55 from ahmedirfan1983/master
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-04-03 Ahmed Irfanappnote for verilog to btor
2015-03-22 Clifford WolfAdded blif reference to appnote 010
2015-02-26 Clifford WolfAdded $assume cell type
2015-02-09 Clifford WolfFixed creation of command reference in manual
2015-02-09 Clifford WolfUpdated command reference in manual
2015-02-09 Clifford WolfVarious presentation fixes
2015-01-19 Clifford WolfAdded $equiv cell type
2014-12-31 Clifford WolfImprovements in CodingReadme
2014-12-08 Clifford WolfAdded more documentation fixmes for nontrivial register...
2014-12-07 Clifford WolfMerge branch 'master' of https://github.com/Martoni...
2014-12-07 Fabien Marteaumanual/presentation.tex: bg option is unknown with...
2014-12-06 Clifford WolfMerge pull request #43 from Martoni/master
2014-12-05 Fabien Marteausuppressing semi-colon at the end of dot files
2014-12-04 Clifford WolfAdded some missing .gitignore in manual/
2014-11-24 Clifford WolfSome fixes in stubnets example
2014-11-08 Clifford WolfSome fixes in presentation
2014-11-08 Clifford WolfVarious documentation updates
2014-11-03 Ahmed Irfancorrected abstract of appnote
2014-11-03 Ahmed Irfanremoved unused bib
2014-11-03 Ahmed Irfancorrections in appnote
2014-11-03 Ahmed Irfanappnote added
2014-10-10 Clifford WolfRenamed SIZE() to GetSize() because of name collision...
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-08 Clifford WolfAdded $lcu cell type
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-09-04 Clifford WolfRemoved $bu0 cell type
2014-09-02 Clifford WolfRemoved references to yosys-svgviewer from docs
2014-08-30 Clifford WolfAdded $alu cell type
2014-08-16 Clifford WolfAdded additional gate types: $_NAND_ $_NOR_ $_XNOR_...
2014-08-15 Clifford WolfRenamed $_INV_ cell type to $_NOT_
2014-08-15 Clifford WolfRemoved old doc references to $safe_pmux
2014-08-14 Clifford WolfRIP $safe_pmux
2014-08-01 Clifford WolfReplaced sha1 implementation
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-31 Clifford WolfRenamed "stdcells.v" to "techmap.v"
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
next