Reformat execute2
[microwatt.git] / microwatt.core
2019-09-12 Anton BlanchardMerge pull request #49 from antonblanchard/icache-2
2019-09-12 Anton BlanchardAdd a simple direct mapped icache
2019-09-10 Benjamin HerrenschmidtShare soc.vhdl between FPGA and sim
2019-09-10 Benjamin HerrenschmidtPass wishbone record to bram memory module
2019-09-10 Benjamin HerrenschmidtSplit FPGA toplevel from soc
2019-09-08 Anton BlanchardMerge pull request #19 from antonblanchard/cmod-a7
2019-09-08 Anton BlanchardCmod A7-35 support
2019-09-08 Anton BlanchardMerge pull request #20 from antonblanchard/reset-rework2
2019-09-07 Anton BlanchardRework SOC reset
2019-09-03 Anton BlanchardMerge pull request #16 from antonblanchard/decode2_rework2
2019-09-03 Anton BlanchardRework decode2
2019-08-29 Anton BlanchardMerge pull request #10 from antonblanchard/arty-fix
2019-08-29 Anton BlanchardArty A7 reset pin is C2
2019-08-29 Anton BlanchardMerge pull request #7 from riktw/fusesoc_arty_a7
2019-08-29 riktwAdded support for building for Arty A7 boards
2019-08-26 Anton BlanchardMerge pull request #3 from olofk/plle2
2019-08-26 Olof KindgrenAdd and use plle2 primitive for nexys boards
2019-08-23 Anton BlanchardMerge pull request #2 from olofk/fusesoc_nexys_a7
2019-08-23 Olof KindgrenAdded synthesis target
2019-08-23 Olof KindgrenAdd Nexys Video support
2019-08-23 Olof KindgrenAdd FuseSoC core description file with Nexys A7 support