| 2019-09-20 |
whitequark | hdl.ast: rename `nbits` to `width`. |
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| 2019-09-20 |
whitequark | back.pysim: fix simulation of Value.xor(). |
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| 2019-09-13 |
whitequark | hdl.ast: add Value.xor, mapping to $reduce_xor. |
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| 2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
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| 2019-09-03 |
whitequark | hdl.ast,back.rtlil: implement Cover. |
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| 2019-08-31 |
whitequark | hdl.cd: add negedge clock domains. |
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| 2019-08-23 |
whitequark | back.pysim: implement sim.add_clock(if_exists=True). locally_working |
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| 2019-08-23 |
whitequark | back.pysim: don't crash when trying to drive a nonexist... |
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| 2019-08-21 |
whitequark | back.pysim: allow coroutines as processes. |
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| 2019-08-19 |
whitequark | lib.cdc: use a local clock domain in ResetSynchronizer. |
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| 2019-08-19 |
whitequark | back.pysim: index domains by identity, not by name. |
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| 2019-08-15 |
whitequark | hdl.ast: implement Initial. |
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| 2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word... |
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| 2019-07-12 |
whitequark | back.pysim: correctly add gtkwave traces for signals... |
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| 2019-07-10 |
whitequark | back.pysim: avoid malformed VCD files when a decoder... |
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| 2019-06-28 |
whitequark | back.pysim: create unique ResetSynchronizer internal... |
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| 2019-06-28 |
whitequark | back.pysim: override ResetSynchronizer implementation. |
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| 2019-06-28 |
whitequark | hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case... |
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| 2019-06-26 |
whitequark | back.pysim: fix scope screwup. |
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| 2019-06-25 |
whitequark | hdl.{ast,dst}: directly represent RTLIL default case. |
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| 2019-06-11 |
whitequark | back.pysim: check for a clock being added twice. |
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| 2019-01-26 |
whitequark | back.pysim: support async reset. |
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| 2019-01-26 |
whitequark | back.pysim: give better names to unnamed fragments... |
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| 2019-01-26 |
whitequark | hdl.ir: rename .get_fragment() to .elaborate(). |
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| 2019-01-25 |
whitequark | back.pysim: fix behavior of initial cycle for sync... |
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| 2019-01-21 |
whitequark | back.pysim: wake up processes before ever committing... |
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| 2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer. |
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| 2019-01-15 |
William D. Jones | hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method... |
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| 2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals. |
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| 2019-01-06 |
Adam Greig | Give the top level scope a name to fix VCD hierarchy. |
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| 2019-01-02 |
William D. Jones | hdl.xfrm: Add Assert and Assume abstract methods for... |
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| 2018-12-29 |
whitequark | back.pysim: warn if simulation is not run. |
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| 2018-12-28 |
whitequark | hdl.rec: add basic record support. |
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| 2018-12-26 |
whitequark | lib.cdc: add tests for MultiReg. |
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| 2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor |
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| 2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
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| 2018-12-21 |
whitequark | back.pysim: give numeric names to unnamed subfragments... |
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| 2018-12-21 |
whitequark | back.pysim: fix an issue with too few funclet slots. |
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| 2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts} |
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| 2018-12-18 |
whitequark | back.pysim: implement *. |
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| 2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors. |
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| 2018-12-18 |
whitequark | back.pysim: eliminate most dictionary lookups. |
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| 2018-12-18 |
whitequark | back.pysim: use arrays instead of dicts for signal... |
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| 2018-12-18 |
whitequark | back.pysim: naming. NFC. |
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| 2018-12-18 |
whitequark | back.pysim: fix an off-by-1 in add_sync_process(). |
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| 2018-12-18 |
whitequark | back.pysim: trigger processes waiting on Tick() exactly... |
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| 2018-12-18 |
whitequark | back.pysim: continue running simulator processes until... |
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| 2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict. |
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| 2018-12-16 |
whitequark | hdl.xfrm: separate AST traversal from AST identity... |
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| 2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
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| 2018-12-15 |
whitequark | back.pysim: add (stub) LHSValueCompiler. |
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| 2018-12-15 |
whitequark | back.pysim: implement Part. |
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| 2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
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| 2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
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| 2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
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| 2018-12-15 |
whitequark | Consistently use '{!r}' in and only in TypeError messages. |
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| 2018-12-14 |
whitequark | back.pysim: preserve process locations through add_sync... |
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| 2018-12-14 |
whitequark | back.pysim: count delta cycles separately to avoid... |
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| 2018-12-14 |
whitequark | back.pysim: simplify. |
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| 2018-12-14 |
whitequark | back.pysim: revert 70ebc6f2. |
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| 2018-12-14 |
whitequark | back.pysim: fix implicit boolean conversion. |
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| 2018-12-14 |
whitequark | back.pysim: squash one level of hierarchy. |
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| 2018-12-14 |
whitequark | back.pysim: implement blocking assignment semantics... |
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| 2018-12-14 |
whitequark | back.pysim: undriven sync signals should return to... |
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| 2018-12-14 |
whitequark | back.pysim: in simulator sync processes, start by waiti... |
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| 2018-12-14 |
whitequark | back.pysim: make initial phase configurable. |
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| 2018-12-14 |
whitequark | pysim.back: fix add_sync_process wrapper to handle... |
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| 2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
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| 2018-12-14 |
whitequark | back.pysim: better naming. NFC. |
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| 2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
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| 2018-12-14 |
whitequark | back.pysim: close .vcd/.gtkw files on context manager... |
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| 2018-12-14 |
whitequark | back.pysim: show more legible names for processes in... |
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| 2018-12-14 |
whitequark | back.pysim: throw exceptions back at processes. |
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| 2018-12-14 |
whitequark | back.pysim: add gtkw traces even more robustly. |
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| 2018-12-14 |
whitequark | back.pysim: accept (and evaluate) generator functions. |
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| 2018-12-14 |
whitequark | back.pysim: skip VCD signal population if VCD is not... |
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| 2018-12-14 |
whitequark | back.pysim: allow processes to evaluate expressions. |
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| 2018-12-14 |
whitequark | back.pysim: more general clean-up. |
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| 2018-12-14 |
whitequark | back.pysim: general clean-up. |
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| 2018-12-14 |
whitequark | back.pysim: accept any valid assignments from processes. |
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| 2018-12-14 |
whitequark | back.pysim: robustly retrieve vcd names for clk/rst... |
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| 2018-12-14 |
whitequark | back.pysim: undriven comb signals should return to... |
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| 2018-12-14 |
whitequark | ast, back.pysim: allow specifying user-defined decoders... |
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| 2018-12-14 |
whitequark | back.pysim: fix completely broken codegen for Switch. |
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| 2018-12-14 |
whitequark | back.pysim: raise an exception if delta cycles blow... |
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| 2018-12-14 |
whitequark | back.pysim: if requested, write a gtkw file with a... |
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| 2018-12-14 |
whitequark | back.pysim: explain how delta cycles work. |
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| 2018-12-14 |
whitequark | back.pysim: delay clock processes by one half period. |
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| 2018-12-14 |
whitequark | back.pysim: implement "sync processes", like migen... |
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| 2018-12-14 |
whitequark | back.pysim: allow suspending processes until a tick... |
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| 2018-12-14 |
whitequark | back.pysim: use bare ints for signal values (-5% runtime). |
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| 2018-12-13 |
whitequark | back.pysim: collect handlers before running (-5% runtime). |
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| 2018-12-13 |
whitequark | back.pysim: allow multiple registered handlers per... |
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| 2018-12-13 |
whitequark | back.pysim: fix handling of process termination. |
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| 2018-12-13 |
whitequark | back.pysim: new simulator backend (WIP). |
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projects / nmigen.git / history