2020-07-15 |
whitequark | back.rtlil: fix guard for division by zero. |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim→sim.pysim; split into more manageable parts. |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim: only extract signal names if VCD is requested. |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim: reset timeline as well. |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim: simplify. NFC. |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim: extract timeline handling to class _Timelin... |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim: extract simulator commands to sim._cmds... |
tree | commitdiff |
2020-07-08 |
whitequark | back.pysim: simplify. NFC. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: simplify. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: simplify. NFC. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: simplify. NFC. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: synchronize waveform writing with cxxrtl. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: synchronize terms with cxxrtl. NFC. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: simplify. NFC. |
tree | commitdiff |
2020-07-07 |
whitequark | back.pysim: simplify. NFC. |
tree | commitdiff |
2020-07-07 |
whitequark | Remove everything deprecated in nmigen 0.2. |
tree | commitdiff |
2020-07-02 |
whitequark | _yosys→_toolchain.yosys |
tree | commitdiff |
2020-06-28 |
whitequark | back.pysim: simplify. |
tree | commitdiff |
2020-06-14 |
whitequark | back.verilog: refactor Yosys script generation. NFCI. |
tree | commitdiff |
2020-06-14 |
whitequark | back.cxxrtl: allow injecting black boxes. |
tree | commitdiff |
2020-06-11 |
whitequark | back.cxxrtl: new backend. |
tree | commitdiff |
2020-06-11 |
whitequark | _yosys: translate Yosys warnings to Python warnings. |
tree | commitdiff |
2020-06-11 |
whitequark | back.verilog: remove unused imports. NFC. |
tree | commitdiff |
2020-05-22 |
whitequark | back.verilog: fall back to nmigen_yosys package. |
tree | commitdiff |
2020-05-19 |
whitequark | back.rtlil: handle signed and large Instance parameters... |
tree | commitdiff |
2020-04-28 |
whitequark | back.rtlil: fix incorrect escaping of signed parameters. |
tree | commitdiff |
2020-04-23 |
Teguh Hofstee | back.verilog: add workaround for evaluation Verific... |
tree | commitdiff |
2020-04-22 |
Teguh Hofstee | back.verilog: make Yosys version check compatible with... |
tree | commitdiff |
2020-04-16 |
anuejn | hdl.rec: make Record inherit from UserValue. working_23jun2020 |
tree | commitdiff |
2020-04-15 |
whitequark | back.rtlil: translate enum decoders to Yosys enum attri... |
tree | commitdiff |
2020-04-13 |
whitequark | back.rtlil: don't emit connections to zero width ports. |
tree | commitdiff |
2020-04-13 |
whitequark | back.rtlil: refuse to create extremely large wires. |
tree | commitdiff |
2020-04-13 |
whitequark | back.rtlil: fix expansion of Part() for partial dummy... |
tree | commitdiff |
2020-04-13 |
whitequark | back.rtlil: fix legalization of Part() with stride. |
tree | commitdiff |
2020-04-13 |
whitequark | Clarify a few comments. NFC. |
tree | commitdiff |
2020-04-08 |
Stuart Olsen | back.pysim: Clear pending updates after they are effected |
tree | commitdiff |
2020-04-07 |
Stuart Olsen | back.pysim: Eliminate duplicate dict lookup in VCD... |
tree | commitdiff |
2020-04-07 |
Stuart Olsen | back.pysim: Reuse clock simulation commands |
tree | commitdiff |
2020-04-03 |
whitequark | back.pysim: fix emission of undriven traces to VCD... |
tree | commitdiff |
2020-03-15 |
Stuart Olsen | back.pysim: implement modulus operator. |
tree | commitdiff |
2020-02-19 |
whitequark | back.pysim: fix RHS codegen for Cat() and Repl(...... |
tree | commitdiff |
2020-02-19 |
whitequark | back.pysim: optionally allow introspecting generated... |
tree | commitdiff |
2020-02-12 |
whitequark | back.pysim: accept write_vcd(vcd_file=None). |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
tree | commitdiff |
2020-02-06 |
whitequark | back.pysim: emit toplevel inputs in VCD files as well. |
tree | commitdiff |
2020-02-06 |
whitequark | back.pysim: make `write_vcd(traces=)` actually use... |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value. |
tree | commitdiff |
2020-01-31 |
whitequark | back.rtlil: don't emit wires for empty signals. |
tree | commitdiff |
2020-01-01 |
whitequark | back.rtlil: do not consider unreachable array elements... |
tree | commitdiff |
2019-12-02 |
whitequark | back.pysim: fix miscompilation of Signal(unsigned)... |
tree | commitdiff |
2019-11-28 |
whitequark | back.pysim: redesign the simulator. |
tree | commitdiff |
2019-11-27 |
whitequark | back.rtlil: infer bit width for instance parameters. |
tree | commitdiff |
2019-11-18 |
whitequark | back.rtlil: extend shorter operand of a binop when... |
tree | commitdiff |
2019-10-28 |
whitequark | back.verilog: remove $verilog_initial_trigger after... |
tree | commitdiff |
2019-10-26 |
whitequark | back.rtlil: avoid exponential behavior when legalizing... |
tree | commitdiff |
2019-10-26 |
whitequark | back.rtlil: fix lowering of Part() on LHS to account... |
tree | commitdiff |
2019-10-16 |
Sebastien Bourdeauducq | verilog: fix yosys version error message |
tree | commitdiff |
2019-10-16 |
whitequark | back.verilog: fix Yosys version check. |
tree | commitdiff |
2019-10-13 |
whitequark | {,_}tools→{,_}utils |
tree | commitdiff |
2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop. |
tree | commitdiff |
2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
tree | commitdiff |
2019-10-12 |
Jean-François Nguyen | back.rtlil: fix DeprecationWarning. NFC. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor... |
tree | commitdiff |
2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: Operator.{op→operator} |
tree | commitdiff |
2019-10-10 |
whitequark | vendor.intel: add Quartus support. |
tree | commitdiff |
2019-10-06 |
whitequark | back.rtlil: don't crash legalizing values with no branches. |
tree | commitdiff |
2019-10-04 |
whitequark | back.rtlil: avoid unsoundness for division by zero. |
tree | commitdiff |
2019-10-02 |
whitequark | back.rtlil: don't cache wires for legalized switch... |
tree | commitdiff |
2019-10-02 |
whitequark | back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow... |
tree | commitdiff |
2019-10-02 |
whitequark | back.rtlil: it is not necessary to match binop operand... |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
tree | commitdiff |
2019-09-24 |
whitequark | back.rtlil: fix handling of certain nested arrays. |
tree | commitdiff |
2019-09-24 |
whitequark | build.plat: strip internal attributes from Verilog... |
tree | commitdiff |
2019-09-23 |
whitequark | back.rtlil: give predictable names to anonymous subfrag... |
tree | commitdiff |
2019-09-20 |
whitequark | hdl.ast: rename `nbits` to `width`. |
tree | commitdiff |
2019-09-20 |
whitequark | back.pysim: fix simulation of Value.xor(). |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.xor, mapping to $reduce_xor. |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
tree | commitdiff |
2019-09-11 |
whitequark | back: return name map from convert_fragment(). |
tree | commitdiff |
2019-09-03 |
whitequark | hdl.ast,back.rtlil: implement Cover. |
tree | commitdiff |
2019-08-31 |
whitequark | hdl.cd: add negedge clock domains. |
tree | commitdiff |
2019-08-31 |
Emily | _toolchain,build.plat,vendor.*: add required_tools... |
tree | commitdiff |
2019-08-28 |
whitequark | _toolchain: new module, for injecting dependencies... |
tree | commitdiff |
2019-08-26 |
whitequark | back.verilog: bump Yosys version requirement to 0.9. |
tree | commitdiff |
2019-08-23 |
whitequark | back.pysim: implement sim.add_clock(if_exists=True). locally_working |
tree | commitdiff |
2019-08-23 |
whitequark | back.pysim: don't crash when trying to drive a nonexist... |
tree | commitdiff |
2019-08-22 |
whitequark | back.rtlil: print real parameters with maximum precision. |
tree | commitdiff |
2019-08-22 |
Darrell Harmon | back.rtlil: add support for real (float) parameters... |
tree | commitdiff |
2019-08-21 |
whitequark | back.pysim: allow coroutines as processes. |
tree | commitdiff |
2019-08-19 |
whitequark | back.verilog: parse output of `yosys -V`. |
tree | commitdiff |
2019-08-19 |
whitequark | lib.cdc: use a local clock domain in ResetSynchronizer. |
tree | commitdiff |
2019-08-19 |
whitequark | back.pysim: index domains by identity, not by name. |
tree | commitdiff |
2019-08-19 |
whitequark | back.{rtlil,verilog}: split convert_fragment() off... |
tree | commitdiff |
2019-08-15 |
whitequark | hdl.ast: implement Initial. |
tree | commitdiff |
2019-08-04 |
whitequark | back.rtlil: use a dummy wire, not 'x, when assigning... |
tree | commitdiff |
2019-08-03 |
whitequark | back.rtlil: actually match shape of left hand side. |
tree | commitdiff |
2019-08-03 |
whitequark | back.rtlil: fix sim-synth mismatch with assigns followi... |
tree | commitdiff |
2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word... |
tree | commitdiff |
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