compat.genlib.fsm: fix naming for non-Signal LHS.
[nmigen.git] / nmigen / back /
2018-12-22 whitequarkback.rtlil: split processes as finely as possible.
2018-12-22 whitequarkback.rtlil: remove useless condition. NFC.
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor
2018-12-22 whitequarkback.rtlil: always initialize the entire memory.
2018-12-22 whitequarkback.verilog: do not rename internal signals.
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes.
2018-12-21 whitequarkback.pysim: give numeric names to unnamed subfragments...
2018-12-21 whitequarkback.pysim: fix an issue with too few funclet slots.
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa...
2018-12-21 whitequarkback.rtlil: more consistent prefixing for subfragment...
2018-12-21 whitequarkback.rtlil: implement memories.
2018-12-21 whitequarkback.rtlil: explicitly pad constants with zeroes.
2018-12-21 whitequarkback.rtlil: fix translation of Cat.
2018-12-20 whitequarkir: allow non-Signals in Instance ports.
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts}
2018-12-18 whitequarkback.pysim: implement *.
2018-12-18 whitequarktest.sim: add tests for sync functionality and errors.
2018-12-18 whitequarkback.pysim: eliminate most dictionary lookups.
2018-12-18 whitequarkback.pysim: use arrays instead of dicts for signal...
2018-12-18 whitequarkback.pysim: naming. NFC.
2018-12-18 whitequarkback.pysim: fix an off-by-1 in add_sync_process().
2018-12-18 whitequarkback.pysim: trigger processes waiting on Tick() exactly...
2018-12-18 whitequarkback.pysim: continue running simulator processes until...
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters...
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict.
2018-12-17 whitequarkback.rtlil: update for Yosys master.
2018-12-17 whitequarkback.rtlil: implement Array.
2018-12-17 whitequarkback.rtlil: implement Part.
2018-12-16 whitequarkback.rtlil: handle reset_less domains.
2018-12-16 whitequarkback.rtlil: extract _StatementCompiler. NFC.
2018-12-16 whitequarkback.rtlil: simplify. NFC.
2018-12-16 whitequarkback.rtlil: properly escape strings in attributes.
2018-12-16 whitequarkback.rtlil: prepare for Yosys sigspec slicing improvements.
2018-12-16 whitequarkback.rtlil: avoid illegal slices.
2018-12-16 whitequarkback.rtlil: use slicing to match shape when reducing...
2018-12-16 whitequarkback.rtlil: don't emit a slice if all bits are used.
2018-12-16 whitequarkback.rtlil: reorganize value compiler into LHS/RHS.
2018-12-16 whitequarkback.rtlil: fix naming. NFC.
2018-12-16 whitequarkhdl.xfrm: separate AST traversal from AST identity...
2018-12-16 whitequarkback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy.
2018-12-15 whitequarkback.pysim: add (stub) LHSValueCompiler.
2018-12-15 whitequarkback.pysim: implement Part.
2018-12-15 whitequarkback.pysim: implement ArrayProxy.
2018-12-15 whitequarkRename fhdl→hdl, genlib→lib.
2018-12-15 whitequarkfhdl.ast, back.pysim: implement shifts.
2018-12-15 whitequarkConsistently use '{!r}' in and only in TypeError messages.
2018-12-14 whitequarkback.pysim: preserve process locations through add_sync...
2018-12-14 whitequarkback.pysim: count delta cycles separately to avoid...
2018-12-14 whitequarkback.pysim: simplify.
2018-12-14 whitequarkback.pysim: revert 70ebc6f2.
2018-12-14 whitequarkback.pysim: fix implicit boolean conversion.
2018-12-14 whitequarkback.pysim: squash one level of hierarchy.
2018-12-14 whitequarkback.pysim: implement blocking assignment semantics...
2018-12-14 whitequarkback.pysim: undriven sync signals should return to...
2018-12-14 whitequarkback.pysim: in simulator sync processes, start by waiti...
2018-12-14 whitequarkback.pysim: make initial phase configurable.
2018-12-14 whitequarkpysim.back: fix add_sync_process wrapper to handle...
2018-12-14 whitequarkback.pysim: Simulator({gtkw_signals→traces}=).
2018-12-14 whitequarkback.pysim: better naming. NFC.
2018-12-14 whitequarkback.pysim: implement most operators and add tests.
2018-12-14 whitequarkback.pysim: close .vcd/.gtkw files on context manager...
2018-12-14 whitequarkback.pysim: show more legible names for processes in...
2018-12-14 whitequarkback.pysim: throw exceptions back at processes.
2018-12-14 whitequarkback.pysim: add gtkw traces even more robustly.
2018-12-14 whitequarkback.pysim: accept (and evaluate) generator functions.
2018-12-14 whitequarkback.pysim: skip VCD signal population if VCD is not...
2018-12-14 whitequarkback.pysim: allow processes to evaluate expressions.
2018-12-14 whitequarkback.pysim: more general clean-up.
2018-12-14 whitequarkback.pysim: general clean-up.
2018-12-14 whitequarkback.pysim: accept any valid assignments from processes.
2018-12-14 whitequarkback.pysim: robustly retrieve vcd names for clk/rst...
2018-12-14 whitequarkback.pysim: undriven comb signals should return to...
2018-12-14 whitequarkast, back.pysim: allow specifying user-defined decoders...
2018-12-14 whitequarkback.pysim: fix completely broken codegen for Switch.
2018-12-14 whitequarkback.pysim: raise an exception if delta cycles blow...
2018-12-14 whitequarkback.pysim: if requested, write a gtkw file with a...
2018-12-14 whitequarkback.pysim: explain how delta cycles work.
2018-12-14 whitequarkback.pysim: delay clock processes by one half period.
2018-12-14 whitequarkback.pysim: implement "sync processes", like migen...
2018-12-14 whitequarkback.pysim: allow suspending processes until a tick...
2018-12-14 whitequarkback.pysim: use bare ints for signal values (-5% runtime).
2018-12-13 whitequarkback.pysim: collect handlers before running (-5% runtime).
2018-12-13 whitequarkback.pysim: allow multiple registered handlers per...
2018-12-13 whitequarkback.pysim: fix handling of process termination.
2018-12-13 whitequarkback.pysim: new simulator backend (WIP).
2018-12-13 whitequarkfhdl.ir: move Fragment prepare logic from back.rtlil.
2018-12-13 whitequarkback.verilog: remove debug code.
2018-12-13 whitequarkfhdl.ir: record port direction explicitly.
2018-12-13 whitequarkcompat.genlib.fsm: import/wrap Migen code.
2018-12-13 whitequarkfhdl, back: trace and emit source locations of values.
2018-12-13 whitequarkback.rtlil: never give subfragment cells names starting...
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation.
2018-12-13 whitequarkfhdl.ir: remove iter_domains().
2018-12-13 whitequarkfhdl: cd_name→domain.
2018-12-13 whitequarkfhdl.cd: rename ClockDomain.{reset→rst}.
2018-12-13 whitequarkback.verilog: detect undriven public wires using Yosys.
2018-12-13 whitequarkback.rtlil: fix swapped operands in sync assign.
2018-12-13 whitequarkback.rtlil: explain logic for CD reset insertion.
2018-12-13 whitequarkback.rtlil: explicitly set the top module.
2018-12-13 whitequarkfhdl.ir: explain how port enumeration works.
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