2018-12-22 |
whitequark | back.rtlil: split processes as finely as possible. |
tree | commitdiff |
2018-12-22 |
whitequark | back.rtlil: remove useless condition. NFC. |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor |
tree | commitdiff |
2018-12-22 |
whitequark | back.rtlil: always initialize the entire memory. |
tree | commitdiff |
2018-12-22 |
whitequark | back.verilog: do not rename internal signals. |
tree | commitdiff |
2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
tree | commitdiff |
2018-12-21 |
whitequark | back.pysim: give numeric names to unnamed subfragments... |
tree | commitdiff |
2018-12-21 |
whitequark | back.pysim: fix an issue with too few funclet slots. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: tie rdport.en high for asynchronous or transpa... |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: more consistent prefixing for subfragment... |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: implement memories. |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: explicitly pad constants with zeroes. |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: fix translation of Cat. |
tree | commitdiff |
2018-12-20 |
whitequark | ir: allow non-Signals in Instance ports. |
tree | commitdiff |
2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts} |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: implement *. |
tree | commitdiff |
2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors. |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: eliminate most dictionary lookups. |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: use arrays instead of dicts for signal... |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: naming. NFC. |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: fix an off-by-1 in add_sync_process(). |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: trigger processes waiting on Tick() exactly... |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: continue running simulator processes until... |
tree | commitdiff |
2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters... |
tree | commitdiff |
2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: update for Yosys master. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: implement Array. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: implement Part. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: handle reset_less domains. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: extract _StatementCompiler. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: simplify. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: properly escape strings in attributes. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: prepare for Yosys sigspec slicing improvements. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: avoid illegal slices. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: use slicing to match shape when reducing... |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: don't emit a slice if all bits are used. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: reorganize value compiler into LHS/RHS. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: fix naming. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | hdl.xfrm: separate AST traversal from AST identity... |
tree | commitdiff |
2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: add (stub) LHSValueCompiler. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: implement Part. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
tree | commitdiff |
2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
tree | commitdiff |
2018-12-15 |
whitequark | Consistently use '{!r}' in and only in TypeError messages. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: preserve process locations through add_sync... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: count delta cycles separately to avoid... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: simplify. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: revert 70ebc6f2. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: fix implicit boolean conversion. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: squash one level of hierarchy. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: implement blocking assignment semantics... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: undriven sync signals should return to... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: in simulator sync processes, start by waiti... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: make initial phase configurable. |
tree | commitdiff |
2018-12-14 |
whitequark | pysim.back: fix add_sync_process wrapper to handle... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: better naming. NFC. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: close .vcd/.gtkw files on context manager... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: show more legible names for processes in... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: throw exceptions back at processes. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: add gtkw traces even more robustly. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: accept (and evaluate) generator functions. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: skip VCD signal population if VCD is not... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: allow processes to evaluate expressions. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: more general clean-up. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: general clean-up. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: accept any valid assignments from processes. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: robustly retrieve vcd names for clk/rst... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: undriven comb signals should return to... |
tree | commitdiff |
2018-12-14 |
whitequark | ast, back.pysim: allow specifying user-defined decoders... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: fix completely broken codegen for Switch. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: raise an exception if delta cycles blow... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: if requested, write a gtkw file with a... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: explain how delta cycles work. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: delay clock processes by one half period. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: implement "sync processes", like migen... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: allow suspending processes until a tick... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: use bare ints for signal values (-5% runtime). |
tree | commitdiff |
2018-12-13 |
whitequark | back.pysim: collect handlers before running (-5% runtime). |
tree | commitdiff |
2018-12-13 |
whitequark | back.pysim: allow multiple registered handlers per... |
tree | commitdiff |
2018-12-13 |
whitequark | back.pysim: fix handling of process termination. |
tree | commitdiff |
2018-12-13 |
whitequark | back.pysim: new simulator backend (WIP). |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ir: move Fragment prepare logic from back.rtlil. |
tree | commitdiff |
2018-12-13 |
whitequark | back.verilog: remove debug code. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ir: record port direction explicitly. |
tree | commitdiff |
2018-12-13 |
whitequark | compat.genlib.fsm: import/wrap Migen code. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl, back: trace and emit source locations of values. |
tree | commitdiff |
2018-12-13 |
whitequark | back.rtlil: never give subfragment cells names starting... |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ir: implement clock domain propagation. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ir: remove iter_domains(). |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl: cd_name→domain. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.cd: rename ClockDomain.{reset→rst}. |
tree | commitdiff |
2018-12-13 |
whitequark | back.verilog: detect undriven public wires using Yosys. |
tree | commitdiff |
2018-12-13 |
whitequark | back.rtlil: fix swapped operands in sync assign. |
tree | commitdiff |
2018-12-13 |
whitequark | back.rtlil: explain logic for CD reset insertion. |
tree | commitdiff |
2018-12-13 |
whitequark | back.rtlil: explicitly set the top module. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ir: explain how port enumeration works. |
tree | commitdiff |
next |