2020-02-12 |
whitequark | back.pysim: accept write_vcd(vcd_file=None). |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
tree | commitdiff |
2020-02-06 |
whitequark | back.pysim: emit toplevel inputs in VCD files as well. |
tree | commitdiff |
2020-02-06 |
whitequark | back.pysim: make `write_vcd(traces=)` actually use... |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value. |
tree | commitdiff |
2020-01-31 |
whitequark | back.rtlil: don't emit wires for empty signals. |
tree | commitdiff |
2020-01-01 |
whitequark | back.rtlil: do not consider unreachable array elements... |
tree | commitdiff |
2019-12-02 |
whitequark | back.pysim: fix miscompilation of Signal(unsigned)... |
tree | commitdiff |
2019-11-28 |
whitequark | back.pysim: redesign the simulator. |
tree | commitdiff |
2019-11-27 |
whitequark | back.rtlil: infer bit width for instance parameters. |
tree | commitdiff |
2019-11-18 |
whitequark | back.rtlil: extend shorter operand of a binop when... |
tree | commitdiff |
2019-10-28 |
whitequark | back.verilog: remove $verilog_initial_trigger after... |
tree | commitdiff |
2019-10-26 |
whitequark | back.rtlil: avoid exponential behavior when legalizing... |
tree | commitdiff |
2019-10-26 |
whitequark | back.rtlil: fix lowering of Part() on LHS to account... |
tree | commitdiff |
2019-10-16 |
Sebastien Bourdeauducq | verilog: fix yosys version error message |
tree | commitdiff |
2019-10-16 |
whitequark | back.verilog: fix Yosys version check. |
tree | commitdiff |
2019-10-13 |
whitequark | {,_}tools→{,_}utils |
tree | commitdiff |
2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop. |
tree | commitdiff |
2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
tree | commitdiff |
2019-10-12 |
Jean-François Nguyen | back.rtlil: fix DeprecationWarning. NFC. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor... |
tree | commitdiff |
2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: Operator.{op→operator} |
tree | commitdiff |
2019-10-10 |
whitequark | vendor.intel: add Quartus support. |
tree | commitdiff |
2019-10-06 |
whitequark | back.rtlil: don't crash legalizing values with no branches. |
tree | commitdiff |
2019-10-04 |
whitequark | back.rtlil: avoid unsoundness for division by zero. |
tree | commitdiff |
2019-10-02 |
whitequark | back.rtlil: don't cache wires for legalized switch... |
tree | commitdiff |
2019-10-02 |
whitequark | back.rtlil: sign of rhs and lhs of ${sshr,sshl,pow... |
tree | commitdiff |
2019-10-02 |
whitequark | back.rtlil: it is not necessary to match binop operand... |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
tree | commitdiff |
2019-09-24 |
whitequark | back.rtlil: fix handling of certain nested arrays. |
tree | commitdiff |
2019-09-24 |
whitequark | build.plat: strip internal attributes from Verilog... |
tree | commitdiff |
2019-09-23 |
whitequark | back.rtlil: give predictable names to anonymous subfrag... |
tree | commitdiff |
2019-09-20 |
whitequark | hdl.ast: rename `nbits` to `width`. |
tree | commitdiff |
2019-09-20 |
whitequark | back.pysim: fix simulation of Value.xor(). |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.xor, mapping to $reduce_xor. |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
tree | commitdiff |
2019-09-11 |
whitequark | back: return name map from convert_fragment(). |
tree | commitdiff |
2019-09-03 |
whitequark | hdl.ast,back.rtlil: implement Cover. |
tree | commitdiff |
2019-08-31 |
whitequark | hdl.cd: add negedge clock domains. |
tree | commitdiff |
2019-08-31 |
Emily | _toolchain,build.plat,vendor.*: add required_tools... |
tree | commitdiff |
2019-08-28 |
whitequark | _toolchain: new module, for injecting dependencies... |
tree | commitdiff |
2019-08-26 |
whitequark | back.verilog: bump Yosys version requirement to 0.9. |
tree | commitdiff |
2019-08-23 |
whitequark | back.pysim: implement sim.add_clock(if_exists=True). locally_working |
tree | commitdiff |
2019-08-23 |
whitequark | back.pysim: don't crash when trying to drive a nonexist... |
tree | commitdiff |
2019-08-22 |
whitequark | back.rtlil: print real parameters with maximum precision. |
tree | commitdiff |
2019-08-22 |
Darrell Harmon | back.rtlil: add support for real (float) parameters... |
tree | commitdiff |
2019-08-21 |
whitequark | back.pysim: allow coroutines as processes. |
tree | commitdiff |
2019-08-19 |
whitequark | back.verilog: parse output of `yosys -V`. |
tree | commitdiff |
2019-08-19 |
whitequark | lib.cdc: use a local clock domain in ResetSynchronizer. |
tree | commitdiff |
2019-08-19 |
whitequark | back.pysim: index domains by identity, not by name. |
tree | commitdiff |
2019-08-19 |
whitequark | back.{rtlil,verilog}: split convert_fragment() off... |
tree | commitdiff |
2019-08-15 |
whitequark | hdl.ast: implement Initial. |
tree | commitdiff |
2019-08-04 |
whitequark | back.rtlil: use a dummy wire, not 'x, when assigning... |
tree | commitdiff |
2019-08-03 |
whitequark | back.rtlil: actually match shape of left hand side. |
tree | commitdiff |
2019-08-03 |
whitequark | back.rtlil: fix sim-synth mismatch with assigns followi... |
tree | commitdiff |
2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word... |
tree | commitdiff |
2019-08-03 |
whitequark | hdl.ast, back.rtlil: add source locations to anonymous... |
tree | commitdiff |
2019-07-12 |
whitequark | back.pysim: correctly add gtkwave traces for signals... |
tree | commitdiff |
2019-07-10 |
whitequark | back.pysim: avoid malformed VCD files when a decoder... |
tree | commitdiff |
2019-07-09 |
whitequark | back.rtlil: add decodings to cases when switching on... |
tree | commitdiff |
2019-07-09 |
whitequark | back.verilog: run proc_prune for much cleaner output. |
tree | commitdiff |
2019-07-09 |
whitequark | hdl.{ast,dsl},back.rtlil: track source locations for... |
tree | commitdiff |
2019-07-08 |
whitequark | build.{dsl,res}: allow platform-dependent attributes... |
tree | commitdiff |
2019-07-08 |
whitequark | back.rtlil: don't name-prefix signals connected to... |
tree | commitdiff |
2019-07-08 |
whitequark | back.rtlil: ignore empty source locations. |
tree | commitdiff |
2019-07-08 |
whitequark | back.rtlil: attach source locations to switches, not... |
tree | commitdiff |
2019-07-08 |
whitequark | back.rtlil: use a more principled approach to attribute... |
tree | commitdiff |
2019-07-03 |
whitequark | back.rtlil: emit \src attributes for processes via... |
tree | commitdiff |
2019-07-02 |
whitequark | back.rtlil: emit \sig$next wires instead of \$next... |
tree | commitdiff |
2019-07-02 |
whitequark | back.rtlil: do not emit $next wires for comb signals. |
tree | commitdiff |
2019-07-01 |
whitequark | back.rtlil: fix Array regression in 32446831. |
tree | commitdiff |
2019-06-28 |
whitequark | back.pysim: create unique ResetSynchronizer internal... |
tree | commitdiff |
2019-06-28 |
whitequark | back.pysim: override ResetSynchronizer implementation. |
tree | commitdiff |
2019-06-28 |
whitequark | hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case... |
tree | commitdiff |
2019-06-28 |
whitequark | hdl.ir, back.rtlil: allow specifying attributes on... |
tree | commitdiff |
2019-06-26 |
whitequark | back.pysim: fix scope screwup. |
tree | commitdiff |
2019-06-25 |
whitequark | hdl.{ast,dst}: directly represent RTLIL default case. |
tree | commitdiff |
2019-06-11 |
whitequark | back.pysim: check for a clock being added twice. |
tree | commitdiff |
2019-06-11 |
whitequark | back.rtlil: mask memory init values. |
tree | commitdiff |
2019-05-26 |
whitequark | back.rtlil: allow specifying platform for convert(). |
tree | commitdiff |
2019-05-13 |
whitequark | back.rtlil: assign undriven signals to their reset... |
tree | commitdiff |
2019-04-22 |
whitequark | back.verilog: allow stripping the src attribute, for... working |
tree | commitdiff |
2019-04-22 |
whitequark | hdl.ir: rework named port handling for Instances. |
tree | commitdiff |
2019-04-21 |
whitequark | back.rtlil: emit `nmigen.hierarchy` attribute. |
tree | commitdiff |
2019-04-21 |
whitequark | back.rtlil: only expand legalized values in Array/Part... |
tree | commitdiff |
2019-04-20 |
whitequark | back.rtlil: allow record slices on LHS. |
tree | commitdiff |
2019-03-28 |
whitequark | back.rtlil: fix off-by-one in Part legalization. |
tree | commitdiff |
2019-01-26 |
whitequark | back.rtlil: accept ast.Const as cell parameter. |
tree | commitdiff |
2019-01-26 |
whitequark | back.pysim: support async reset. |
tree | commitdiff |
2019-01-26 |
whitequark | back.pysim: give better names to unnamed fragments... |
tree | commitdiff |
2019-01-26 |
whitequark | back.rtlil: accept any elaboratable, not just fragments. |
tree | commitdiff |
2019-01-26 |
whitequark | hdl.ir: rename .get_fragment() to .elaborate(). |
tree | commitdiff |
2019-01-25 |
whitequark | back.pysim: fix behavior of initial cycle for sync... |
tree | commitdiff |
2019-01-21 |
whitequark | back.pysim: wake up processes before ever committing... |
tree | commitdiff |
2019-01-19 |
whitequark | hdl.ast: give Assert and Assume their own src_loc. |
tree | commitdiff |
2019-01-18 |
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once. |
tree | commitdiff |
2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer. |
tree | commitdiff |
2019-01-16 |
whitequark | back.rtlil: slightly nicer naming for $next signals... |
tree | commitdiff |
next |