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sim._pyrtl: fix miscompilation of -(Const(0b11, 2).as_signed()).
[nmigen.git] / nmigen / back /
2020-07-22 whitequarkback.rtlil: lower maximum accepted wire size. tree | commitdiff
2020-07-15 whitequarkback.rtlil: fix guard for division by zero. tree | commitdiff
2020-07-08 whitequarkback.pysim→sim.pysim; split into more manageable parts. tree | commitdiff
2020-07-08 whitequarkback.pysim: only extract signal names if VCD is requested. tree | commitdiff
2020-07-08 whitequarkback.pysim: reset timeline as well. tree | commitdiff
2020-07-08 whitequarkback.pysim: simplify. NFC. tree | commitdiff
2020-07-08 whitequarkback.pysim: extract timeline handling to class _Timelin... tree | commitdiff
2020-07-08 whitequarkback.pysim: extract simulator commands to sim._cmds... tree | commitdiff
2020-07-08 whitequarkback.pysim: simplify. NFC. tree | commitdiff
2020-07-07 whitequarkback.pysim: simplify. tree | commitdiff
2020-07-07 whitequarkback.pysim: simplify. NFC. tree | commitdiff
2020-07-07 whitequarkback.pysim: simplify. NFC. tree | commitdiff
2020-07-07 whitequarkback.pysim: synchronize waveform writing with cxxrtl. tree | commitdiff
2020-07-07 whitequarkback.pysim: synchronize terms with cxxrtl. NFC. tree | commitdiff
2020-07-07 whitequarkback.pysim: simplify. NFC. tree | commitdiff
2020-07-07 whitequarkback.pysim: simplify. NFC. tree | commitdiff
2020-07-07 whitequarkRemove everything deprecated in nmigen 0.2. tree | commitdiff
2020-07-02 whitequark_yosys→_toolchain.yosys tree | commitdiff
2020-06-28 whitequarkback.pysim: simplify. tree | commitdiff
2020-06-14 whitequarkback.verilog: refactor Yosys script generation. NFCI. tree | commitdiff
2020-06-14 whitequarkback.cxxrtl: allow injecting black boxes. tree | commitdiff
2020-06-11 whitequarkback.cxxrtl: new backend. tree | commitdiff
2020-06-11 whitequark_yosys: translate Yosys warnings to Python warnings. tree | commitdiff
2020-06-11 whitequarkback.verilog: remove unused imports. NFC. tree | commitdiff
2020-05-22 whitequarkback.verilog: fall back to nmigen_yosys package. tree | commitdiff
2020-05-19 whitequarkback.rtlil: handle signed and large Instance parameters... tree | commitdiff
2020-04-28 whitequarkback.rtlil: fix incorrect escaping of signed parameters. tree | commitdiff
2020-04-23 Teguh Hofsteeback.verilog: add workaround for evaluation Verific... tree | commitdiff
2020-04-22 Teguh Hofsteeback.verilog: make Yosys version check compatible with... tree | commitdiff
2020-04-16 anuejnhdl.rec: make Record inherit from UserValue. working_23jun2020 tree | commitdiff
2020-04-15 whitequarkback.rtlil: translate enum decoders to Yosys enum attri... tree | commitdiff
2020-04-13 whitequarkback.rtlil: don't emit connections to zero width ports. tree | commitdiff
2020-04-13 whitequarkback.rtlil: refuse to create extremely large wires. tree | commitdiff
2020-04-13 whitequarkback.rtlil: fix expansion of Part() for partial dummy... tree | commitdiff
2020-04-13 whitequarkback.rtlil: fix legalization of Part() with stride. tree | commitdiff
2020-04-13 whitequarkClarify a few comments. NFC. tree | commitdiff
2020-04-08 Stuart Olsenback.pysim: Clear pending updates after they are effected tree | commitdiff
2020-04-07 Stuart Olsenback.pysim: Eliminate duplicate dict lookup in VCD... tree | commitdiff
2020-04-07 Stuart Olsenback.pysim: Reuse clock simulation commands tree | commitdiff
2020-04-03 whitequarkback.pysim: fix emission of undriven traces to VCD... tree | commitdiff
2020-03-15 Stuart Olsenback.pysim: implement modulus operator. tree | commitdiff
2020-02-19 whitequarkback.pysim: fix RHS codegen for Cat() and Repl(...... tree | commitdiff
2020-02-19 whitequarkback.pysim: optionally allow introspecting generated... tree | commitdiff
2020-02-12 whitequarkback.pysim: accept write_vcd(vcd_file=None). tree | commitdiff
2020-02-06 whitequarkhdl.ast: add Value.{as_signed,as_unsigned}. tree | commitdiff
2020-02-06 whitequarkback.pysim: emit toplevel inputs in VCD files as well. tree | commitdiff
2020-02-06 whitequarkback.pysim: make `write_vcd(traces=)` actually use... tree | commitdiff
2020-02-06 whitequarkhdl.mem: add synthesis attribute support. tree | commitdiff
2020-02-01 whitequarkhdl.ast: prohibit shifts by signed value. tree | commitdiff
2020-01-31 whitequarkback.rtlil: don't emit wires for empty signals. tree | commitdiff
2020-01-01 whitequarkback.rtlil: do not consider unreachable array elements... tree | commitdiff
2019-12-02 whitequarkback.pysim: fix miscompilation of Signal(unsigned)... tree | commitdiff
2019-11-28 whitequarkback.pysim: redesign the simulator. tree | commitdiff
2019-11-27 whitequarkback.rtlil: infer bit width for instance parameters. tree | commitdiff
2019-11-18 whitequarkback.rtlil: extend shorter operand of a binop when... tree | commitdiff
2019-10-28 whitequarkback.verilog: remove $verilog_initial_trigger after... tree | commitdiff
2019-10-26 whitequarkback.rtlil: avoid exponential behavior when legalizing... tree | commitdiff
2019-10-26 whitequarkback.rtlil: fix lowering of Part() on LHS to account... tree | commitdiff
2019-10-16 Sebastien Bourdeauducqverilog: fix yosys version error message tree | commitdiff
2019-10-16 whitequarkback.verilog: fix Yosys version check. tree | commitdiff
2019-10-13 whitequark{,_}tools→{,_}utils tree | commitdiff
2019-10-12 whitequarkhdl.ast: rename Slice.end back to Slice.stop. tree | commitdiff
2019-10-12 whitequark_tools: extract most utility methods to a private package. tree | commitdiff
2019-10-12 Jean-François Nguyenback.rtlil: fix DeprecationWarning. NFC. tree | commitdiff
2019-10-11 whitequarkhdl.ast: deprecate shapes like `(1, True)` in favor... tree | commitdiff
2019-10-11 whitequarkConsistently use {!r}, not '{!r}' in diagnostics. tree | commitdiff
2019-10-11 whitequarkhdl.ast: Operator.{op→operator} tree | commitdiff
2019-10-10 whitequarkvendor.intel: add Quartus support. tree | commitdiff
2019-10-06 whitequarkback.rtlil: don't crash legalizing values with no branches. tree | commitdiff
2019-10-04 whitequarkback.rtlil: avoid unsoundness for division by zero. tree | commitdiff
2019-10-02 whitequarkback.rtlil: don't cache wires for legalized switch... tree | commitdiff
2019-10-02 whitequarkback.rtlil: sign of rhs and lhs of ${sshr,sshl,pow... tree | commitdiff
2019-10-02 whitequarkback.rtlil: it is not necessary to match binop operand... tree | commitdiff
2019-09-28 whitequarkhdl.ast: actually implement the // operator. tree | commitdiff
2019-09-24 whitequarkback.rtlil: fix handling of certain nested arrays. tree | commitdiff
2019-09-24 whitequarkbuild.plat: strip internal attributes from Verilog... tree | commitdiff
2019-09-23 whitequarkback.rtlil: give predictable names to anonymous subfrag... tree | commitdiff
2019-09-20 whitequarkhdl.ast: rename `nbits` to `width`. tree | commitdiff
2019-09-20 whitequarkback.pysim: fix simulation of Value.xor(). tree | commitdiff
2019-09-13 whitequarkhdl.ast: add Value.xor, mapping to $reduce_xor. tree | commitdiff
2019-09-13 whitequarkhdl.ast: add Value.{any,all}, mapping to $reduce_{or... tree | commitdiff
2019-09-11 whitequarkback: return name map from convert_fragment(). tree | commitdiff
2019-09-03 whitequarkhdl.ast,back.rtlil: implement Cover. tree | commitdiff
2019-08-31 whitequarkhdl.cd: add negedge clock domains. tree | commitdiff
2019-08-31 Emily_toolchain,build.plat,vendor.*: add required_tools... tree | commitdiff
2019-08-28 whitequark_toolchain: new module, for injecting dependencies... tree | commitdiff
2019-08-26 whitequarkback.verilog: bump Yosys version requirement to 0.9. tree | commitdiff
2019-08-23 whitequarkback.pysim: implement sim.add_clock(if_exists=True). locally_working tree | commitdiff
2019-08-23 whitequarkback.pysim: don't crash when trying to drive a nonexist... tree | commitdiff
2019-08-22 whitequarkback.rtlil: print real parameters with maximum precision. tree | commitdiff
2019-08-22 Darrell Harmonback.rtlil: add support for real (float) parameters... tree | commitdiff
2019-08-21 whitequarkback.pysim: allow coroutines as processes. tree | commitdiff
2019-08-19 whitequarkback.verilog: parse output of `yosys -V`. tree | commitdiff
2019-08-19 whitequarklib.cdc: use a local clock domain in ResetSynchronizer. tree | commitdiff
2019-08-19 whitequarkback.pysim: index domains by identity, not by name. tree | commitdiff
2019-08-19 whitequarkback.{rtlil,verilog}: split convert_fragment() off... tree | commitdiff
2019-08-15 whitequarkhdl.ast: implement Initial. tree | commitdiff
2019-08-04 whitequarkback.rtlil: use a dummy wire, not 'x, when assigning... tree | commitdiff
2019-08-03 whitequarkback.rtlil: actually match shape of left hand side. tree | commitdiff
2019-08-03 whitequarkback.rtlil: fix sim-synth mismatch with assigns followi... tree | commitdiff
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