2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer. |
tree | commitdiff |
2019-01-16 |
whitequark | back.rtlil: slightly nicer naming for $next signals... |
tree | commitdiff |
2019-01-16 |
whitequark | back.rtlil: rename \sig$next to $next$sig. |
tree | commitdiff |
2019-01-15 |
whitequark | Unbreak 655d02d5. |
tree | commitdiff |
2019-01-15 |
William D. Jones | back.rtlil: Generate $anyconst and $anyseq cells. |
tree | commitdiff |
2019-01-15 |
William D. Jones | hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method... |
tree | commitdiff |
2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals. |
tree | commitdiff |
2019-01-13 |
whitequark | back.verilog: better error message if Yosys is not... |
tree | commitdiff |
2019-01-08 |
whitequark | back.verilog: remove undriven check. |
tree | commitdiff |
2019-01-06 |
Adam Greig | Give the top level scope a name to fix VCD hierarchy. |
tree | commitdiff |
2019-01-02 |
whitequark | back.rtlil: translate empty slices correctly. |
tree | commitdiff |
2019-01-02 |
William D. Jones | back.rtlil: Generate RTLIL for Assert/Assume statements. |
tree | commitdiff |
2019-01-02 |
William D. Jones | hdl.xfrm: Add Assert and Assume abstract methods for... |
tree | commitdiff |
2019-01-01 |
whitequark | back.rtlil: fix typo. |
tree | commitdiff |
2018-12-31 |
whitequark | back.rtlil: match shape of Array elements to ArrayProxy... |
tree | commitdiff |
2018-12-31 |
whitequark | back.rtlil: fix typo. |
tree | commitdiff |
2018-12-29 |
whitequark | back.pysim: warn if simulation is not run. |
tree | commitdiff |
2018-12-28 |
whitequark | hdl.rec: add basic record support. |
tree | commitdiff |
2018-12-26 |
whitequark | lib.cdc: add tests for MultiReg. |
tree | commitdiff |
2018-12-26 |
whitequark | back.rtlil: clarify $verilog_initial_trigger behavior... |
tree | commitdiff |
2018-12-24 |
whitequark | back.rtlil: unbreak d47c1f8a. |
tree | commitdiff |
2018-12-24 |
whitequark | back.rtlil: use one $meminit cell, not one per word. |
tree | commitdiff |
2018-12-24 |
whitequark | hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. |
tree | commitdiff |
2018-12-24 |
whitequark | hdl.xfrm: implement SwitchCleaner, for pruning empty... |
tree | commitdiff |
2018-12-24 |
whitequark | back.rtlil: always output negative values as two's... |
tree | commitdiff |
2018-12-23 |
whitequark | back.rtlil: emit dummy logic to work around Verilog... |
tree | commitdiff |
2018-12-23 |
whitequark | back.rtlil: do not translate empty fragments. |
tree | commitdiff |
2018-12-23 |
whitequark | back.rtlil: only translate switch tests once. |
tree | commitdiff |
2018-12-23 |
whitequark | back.rtlil: fix swapped operands in mux codegen. |
tree | commitdiff |
2018-12-22 |
whitequark | back.rtlil: split processes as finely as possible. |
tree | commitdiff |
2018-12-22 |
whitequark | back.rtlil: remove useless condition. NFC. |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor |
tree | commitdiff |
2018-12-22 |
whitequark | back.rtlil: always initialize the entire memory. |
tree | commitdiff |
2018-12-22 |
whitequark | back.verilog: do not rename internal signals. |
tree | commitdiff |
2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
tree | commitdiff |
2018-12-21 |
whitequark | back.pysim: give numeric names to unnamed subfragments... |
tree | commitdiff |
2018-12-21 |
whitequark | back.pysim: fix an issue with too few funclet slots. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: tie rdport.en high for asynchronous or transpa... |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: more consistent prefixing for subfragment... |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: implement memories. |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: explicitly pad constants with zeroes. |
tree | commitdiff |
2018-12-21 |
whitequark | back.rtlil: fix translation of Cat. |
tree | commitdiff |
2018-12-20 |
whitequark | ir: allow non-Signals in Instance ports. |
tree | commitdiff |
2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts} |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: implement *. |
tree | commitdiff |
2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors. |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: eliminate most dictionary lookups. |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: use arrays instead of dicts for signal... |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: naming. NFC. |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: fix an off-by-1 in add_sync_process(). |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: trigger processes waiting on Tick() exactly... |
tree | commitdiff |
2018-12-18 |
whitequark | back.pysim: continue running simulator processes until... |
tree | commitdiff |
2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters... |
tree | commitdiff |
2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: update for Yosys master. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: implement Array. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: implement Part. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: handle reset_less domains. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: extract _StatementCompiler. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: simplify. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: properly escape strings in attributes. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: prepare for Yosys sigspec slicing improvements. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: avoid illegal slices. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: use slicing to match shape when reducing... |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: don't emit a slice if all bits are used. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: reorganize value compiler into LHS/RHS. |
tree | commitdiff |
2018-12-16 |
whitequark | back.rtlil: fix naming. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | hdl.xfrm: separate AST traversal from AST identity... |
tree | commitdiff |
2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: add (stub) LHSValueCompiler. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: implement Part. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
tree | commitdiff |
2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
tree | commitdiff |
2018-12-15 |
whitequark | Consistently use '{!r}' in and only in TypeError messages. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: preserve process locations through add_sync... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: count delta cycles separately to avoid... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: simplify. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: revert 70ebc6f2. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: fix implicit boolean conversion. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: squash one level of hierarchy. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: implement blocking assignment semantics... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: undriven sync signals should return to... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: in simulator sync processes, start by waiti... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: make initial phase configurable. |
tree | commitdiff |
2018-12-14 |
whitequark | pysim.back: fix add_sync_process wrapper to handle... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: better naming. NFC. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: close .vcd/.gtkw files on context manager... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: show more legible names for processes in... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: throw exceptions back at processes. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: add gtkw traces even more robustly. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: accept (and evaluate) generator functions. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: skip VCD signal population if VCD is not... |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: allow processes to evaluate expressions. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: more general clean-up. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: general clean-up. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: accept any valid assignments from processes. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: robustly retrieve vcd names for clk/rst... |
tree | commitdiff |
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