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back.{verilog,rtlil}: adjust $verilog_initial_trigger insertion.
[nmigen.git] / nmigen / compat / sim /
2020-08-27 whitequarksim: split into base, core, and engines. tree | commitdiff
2020-04-02 Jacob LifshayAdd support for using non-compat Elaboratable instances... tree | commitdiff
2019-11-28 whitequarkback.pysim: redesign the simulator. tree | commitdiff
2019-08-03 whitequarkhdl.ir: call back from Fragment.prepare if a clock... tree | commitdiff
2019-01-26 whitequarkcompat.sim: fix deprecated stdlib import. tree | commitdiff
2019-01-26 whitequarkhdl.ir: rename .get_fragment() to .elaborate(). tree | commitdiff
2019-01-26 whitequarktest.compat: import tests from Migen as appropriate. tree | commitdiff
2018-12-14 whitequarkback.pysim: make initial phase configurable. tree | commitdiff
2018-12-14 whitequarkcompat.sim: match clock period. tree | commitdiff
2018-12-14 whitequarkcompat: add run_simulation shim. tree | commitdiff