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back.verilog: detect undriven public wires using Yosys.
[nmigen.git] / nmigen / fhdl /
2018-12-13 whitequarkfhdl.ir: explain how port enumeration works. tree | commitdiff
2018-12-13 whitequarkfhdl.ir: make sure clocks and resets of used CDs appear... tree | commitdiff
2018-12-13 whitequarkcompat.fhdl.module: implement finalization. tree | commitdiff
2018-12-13 whitequarkfhdl.ast: bits_sign→shape. tree | commitdiff
2018-12-13 whitequarkfhdl.ast: add tests for most logic. tree | commitdiff
2018-12-12 whitequarkcompat.fhdl.{module,structure}: import/wrap Migen code... tree | commitdiff
2018-12-12 whitequarkfhdl.ast.Signal: implement .like(). tree | commitdiff
2018-12-12 whitequarkfhdl.ir: fix port threading code. tree | commitdiff
2018-12-12 whitequarkfhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix. tree | commitdiff
2018-12-12 whitequarkfhdl.ast.Signal: fix typo. tree | commitdiff
2018-12-12 whitequarkfhdl.ast.Signal: implement attrs field. tree | commitdiff
2018-12-12 whitequarkfhdl.ast.Signal: implement width derivation from min... tree | commitdiff
2018-12-12 whitequarkfhdl.ast.Signal: implement reset_less signals. tree | commitdiff
2018-12-12 whitequarkfhdl.ast.Signal: assign an internal name if tracer... tree | commitdiff
2018-12-12 whitequarkfhdl.dsl: allow f.sync["dom"] as a synonym of f.sync... tree | commitdiff
2018-12-12 whitequarkClockDomain.{rst→reset}, for consistency with ResetInse... tree | commitdiff
2018-12-12 whitequarkInitial commit. tree | commitdiff