| 2019-06-25 |
whitequark | hdl.{ast,dst}: directly represent RTLIL default case. |
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| 2019-06-13 |
whitequark | hdl.ast: tighten assertion in Switch(). |
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| 2019-06-12 |
whitequark | hdl.ast: add name_suffix=".." option to Signal.like(). |
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| 2019-06-11 |
whitequark | hdl.ast: implement values with custom lowering. |
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| 2019-05-12 |
whitequark | hdl: make all public Value classes other than Record... |
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| 2019-04-21 |
whitequark | hdl.ast: accept Signals with identical min/max bounds. |
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| 2019-04-10 |
whitequark | hdl.ast: fix some type checks. |
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| 2019-04-03 |
whitequark | hdl.ast: handle a common typo, such as Signal(1, True). |
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| 2019-03-25 |
whitequark | hdl.ast: fix typo. |
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| 2019-03-03 |
whitequark | tracer: factor out get_var_name(default=). |
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| 2019-01-26 |
whitequark | hdl.ast: fix ValueKey for Cat. |
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| 2019-01-26 |
whitequark | hdl.ast: fix shape calculation for *. |
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| 2019-01-19 |
whitequark | hdl.ast: implement shape for modulo operator. |
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| 2019-01-19 |
whitequark | hdl.ast: add Value.implies. |
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| 2019-01-19 |
whitequark | hdl.ast: give Assert and Assume their own src_loc. |
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| 2019-01-18 |
whitequark | back.rtlil: only emit each AnyConst/AnySeq cell once. |
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| 2019-01-17 |
whitequark | hdl.ast: allow sampling ClockSignal, ResetSignal. |
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| 2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell. |
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| 2019-01-17 |
whitequark | hdl.ast: add Sample. |
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| 2019-01-16 |
whitequark | hdl.ast: fix naming of Signal.like() signals when trace... |
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| 2019-01-15 |
William D. Jones | hdl.ast: Add AnyConst and AnySeq value types. |
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| 2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS. |
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| 2019-01-13 |
whitequark | hdl.dsl: accept (but warn on) cases wider than switch... |
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| 2019-01-02 |
whitequark | hdl.ast: allow slicing [n:n] into n-bit value. |
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| 2019-01-02 |
William D. Jones | hdl.ast: Add Assert and Assign statements. |
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| 2019-01-01 |
whitequark | hdl.ast: experimentally add Value._as_const. |
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| 2018-12-29 |
whitequark | lib.cdc: fix tests to actually run. |
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| 2018-12-28 |
whitequark | tracer: factor out get_src_loc(). |
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| 2018-12-21 |
whitequark | hdl.mem: implement memories. |
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| 2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts} |
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| 2018-12-18 |
whitequark | hdl.ast, hdl.xfrm: various microoptimizations to speed... |
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| 2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters... |
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| 2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict. |
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| 2018-12-17 |
whitequark | hdl.ast: factor out _MappedKeyDict, _MappedKeySet.... |
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| 2018-12-17 |
whitequark | back.rtlil: implement Array. |
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| 2018-12-17 |
whitequark | back.rtlil: implement Part. |
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| 2018-12-16 |
whitequark | compat.fhdl: reexport Array. |
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| 2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
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| 2018-12-15 |
whitequark | back.pysim: implement Part. |
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| 2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
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| 2018-12-15 |
whitequark | hdl.ast: implement Array and ArrayProxy. |
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| 2018-12-15 |
whitequark | hdl.ast: improve ClockSignal, ResetSignal documentation. |
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| 2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
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projects / nmigen.git / history