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hdl.dsl: clarify error message for incorrect nesting.
[nmigen.git]
/
nmigen
/
hdl
/
dsl.py
2019-07-07
whitequark
hdl.dsl: clarify error message for incorrect nesting.
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2019-07-07
whitequark
hdl.dsl: gracefully handle FSM with no states.
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2019-07-03
whitequark
hdl.dsl: fix src_loc_at for FSM state signal.
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2019-07-03
whitequark
back.rtlil: emit \src attributes for processes via...
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2019-06-28
whitequark
hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case...
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2019-06-25
whitequark
hdl.{ast,dst}: directly represent RTLIL default case.
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2019-06-03
whitequark
hdl.dsl: allow adding submodules with computed name...
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2019-04-21
whitequark
hdl.ir: detect elaboratables that are created but not...
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2019-04-09
whitequark
hdl: remove deprecated get_fragment() and lower() methods.
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2019-01-26
whitequark
hdl.ir: rename .get_fragment() to .elaborate().
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2019-01-17
whitequark
hdl.ast: add Past, Stable, Rose, Fell.
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2019-01-13
whitequark
hdl.dsl: cases wider than switch test value are unreach...
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2019-01-13
whitequark
hdl.dsl: accept (but warn on) cases wider than switch...
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2019-01-02
William D. Jones
hdl.dsl: Support Assert and Assume where an Assign...
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2018-12-27
whitequark
hdl.dsl: add support for fsm.ongoing().
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2018-12-26
whitequark
hdl.dsl: forbid m.next= inside of FSM but outside of...
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2018-12-26
whitequark
hdl.dsl: provide generated values for FSMs.
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2018-12-26
whitequark
examples: add an FSM usage example (UART receiver).
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2018-12-26
whitequark
hdl.dsl: add signal decoder to FSM state signal.
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2018-12-26
whitequark
hdl.dsl: implement FSM.
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2018-12-17
whitequark
hdl, back: add and use SignalSet/SignalDict.
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2018-12-16
whitequark
hdl.dsl: add clock domain support.
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2018-12-16
whitequark
hdl.dsl: cleanup. NFC.
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2018-12-15
whitequark
Rename fhdl→hdl, genlib→lib.
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