2020-07-30 |
Adam Greig | hdl.mem: cast reset value for transparent read ports... |
tree | commitdiff |
2020-07-07 |
awygle | hdl.ast: don't inherit Shape from NamedTuple. |
tree | commitdiff |
2020-06-30 |
whitequark | Add (heavily work in progress) documentation. |
tree | commitdiff |
2020-06-06 |
Adam Greig | hdl.xfrm: preserve allow_reset_less when transforming... |
tree | commitdiff |
2020-06-05 |
Shawn Anastasio | hdl.rec: preserve shapes when constructing a layout. |
tree | commitdiff |
2020-05-24 |
Robin Ole Heinemann | hdl.ast: fix typo |
tree | commitdiff |
2020-05-20 |
whitequark | hdl.ast: add const-shift operations. |
tree | commitdiff |
2020-05-19 |
whitequark | hdl.ast: clarify docs for Value.rotate_{left,right}. |
tree | commitdiff |
2020-05-19 |
whitequark | hdl.dsl: check for unique domain name. |
tree | commitdiff |
2020-04-27 |
whitequark | hdl.ast: use SignalSet, not ValueSet, for _[lr]hs_signa... |
tree | commitdiff |
2020-04-24 |
awygle | hdl.ir: typecheck `convert(ports=)` more carefully. |
tree | commitdiff |
2020-04-16 |
anuejn | hdl.rec: make Record inherit from UserValue. working_23jun2020 |
tree | commitdiff |
2020-04-15 |
whitequark | back.rtlil: translate enum decoders to Yosys enum attri... |
tree | commitdiff |
2020-04-13 |
Dan Ravensloft | hdl.ast: add Value.{rotate_left,rotate_right}. |
tree | commitdiff |
2020-04-12 |
whitequark | hdl.rec: improve repr() for Layout. |
tree | commitdiff |
2020-04-12 |
whitequark | hdl.ast: improve repr() for Shape. |
tree | commitdiff |
2020-04-05 |
whitequark | hdl.mem: fix source location of ReadPort.en. |
tree | commitdiff |
2020-03-22 |
whitequark | hdl.ast: implement abs() on values. |
tree | commitdiff |
2020-03-14 |
awygle | Correctly handle resets in AsyncFIFO. |
tree | commitdiff |
2020-03-08 |
awygle | lib.cdc: extract AsyncFFSynchronizer. |
tree | commitdiff |
2020-02-19 |
whitequark | hdl.ast: fix off-by-1 in Initial.__init__(). |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.ast: add Value.{as_signed,as_unsigned}. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.dsl: make referencing undefined FSM states an error. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.ir: type check ports. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.dsl: reject name mismatch in `m.domains.<name>... |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.dsl: type check when adding to m.domains. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.mem: add synthesis attribute support. |
tree | commitdiff |
2020-02-06 |
whitequark | hdl.mem: document Memory. |
tree | commitdiff |
2020-02-04 |
whitequark | hdl.{ast,dsl}: allow whitespace in bit patterns. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.ast: update documentation for Signal. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.ast: prohibit shifts by signed value. |
tree | commitdiff |
2020-02-01 |
whitequark | build.plat: align pipeline with Fragment.prepare(). |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.dsl: don't allow inheriting from Module. |
tree | commitdiff |
2020-02-01 |
whitequark | hdl.ast: warn on unused property statements (Assert... |
tree | commitdiff |
2020-02-01 |
whitequark | _unused: extract must-use logic from hdl.ir. |
tree | commitdiff |
2020-01-31 |
whitequark | hdl.dsl: add missing case width check for Enum values. |
tree | commitdiff |
2020-01-31 |
whitequark | hdl.dsl: make `if m.{If,Elif,Else}(...)` a syntax error. |
tree | commitdiff |
2020-01-18 |
whitequark | hdl.ir: resolve hierarchy conflicts before creating... |
tree | commitdiff |
2020-01-17 |
whitequark | hdl.xfrm: transform drivers as well in DomainRenamer. |
tree | commitdiff |
2020-01-12 |
whitequark | Remove everything deprecated in nmigen 0.1. |
tree | commitdiff |
2020-01-11 |
Staf Verhaegen | Signal: allow to use integral Enum for reset value. |
tree | commitdiff |
2019-12-15 |
whitequark | hdl.mem: fix src_loc_at in ReadPort, WritePort. |
tree | commitdiff |
2019-12-04 |
Marcin Kościelnicki | hdl.ast: Fix width for unary minus operator on signed... |
tree | commitdiff |
2019-12-02 |
whitequark | hdl.ast: actually remove simulator commands. |
tree | commitdiff |
2019-11-26 |
whitequark | hdl.ir: for instance ports, prioritize defs over uses. |
tree | commitdiff |
2019-11-09 |
whitequark | hdl.rec: fix Record.like() being called through a subclass. v0.1 |
tree | commitdiff |
2019-11-09 |
Staf Verhaegen | hdl.rec: make Record(name=) keyword-only. |
tree | commitdiff |
2019-11-07 |
whitequark | hdl.ir: lower domains before resolving hierarchy conflicts. |
tree | commitdiff |
2019-10-26 |
whitequark | test: use `#nmigen:` magic comment instead of monkey... |
tree | commitdiff |
2019-10-26 |
whitequark | hdl.ir: allow disabling UnusedElaboratable warning... |
tree | commitdiff |
2019-10-26 |
whitequark | hdl.ast: simplify {bit,word}_select with constant offset. |
tree | commitdiff |
2019-10-21 |
whitequark | Explicitly restrict prelude imports. |
tree | commitdiff |
2019-10-13 |
whitequark | {,_}tools→{,_}utils |
tree | commitdiff |
2019-10-13 |
whitequark | hdl.ir: allow ClockSignal and ResetSignal in ports. |
tree | commitdiff |
2019-10-13 |
whitequark | hdl.ir: cast instance port connections to Values. |
tree | commitdiff |
2019-10-12 |
whitequark | hdl.ast: rename Slice.end back to Slice.stop. |
tree | commitdiff |
2019-10-12 |
whitequark | _tools: extract most utility methods to a private package. |
tree | commitdiff |
2019-10-11 |
whitequark | Rename remaining `wrap` methods to `cast`. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate shapes like `(1, True)` in favor... |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: deprecate Signal.{range,enum}. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: add an explicit Shape class, included in prelude. |
tree | commitdiff |
2019-10-11 |
whitequark | Consistently use {!r}, not '{!r}' in diagnostics. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: Operator.{op→operator} |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: simplify enum handling. |
tree | commitdiff |
2019-10-11 |
whitequark | hdl.ast: Value.{wrap→cast} |
tree | commitdiff |
2019-10-09 |
whitequark | build.plat: elaborate result of create_missing_domain... |
tree | commitdiff |
2019-10-04 |
whitequark | hdl.ast: prohibit signed divisors. |
tree | commitdiff |
2019-10-02 |
whitequark | hdl.ast: don't crash on Mux(<bool>, ...). |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.ast: actually implement the // operator. |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.dsl: add a diagnostic for `m.d.submodules += ...`. |
tree | commitdiff |
2019-09-28 |
whitequark | hdl.mem: remove WritePort(priority=) argument. |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.ast: cast Mux() selector to bool if it is not a... |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.mem,lib.fifo: use keyword-only arguments for memory... |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.mem: simplify. NFC. |
tree | commitdiff |
2019-09-23 |
whitequark | hdl.ast: make Signal(name=) a keyword-only argument. |
tree | commitdiff |
2019-09-22 |
whitequark | hdl.rec: fix using Enum subclass as shape if direction... |
tree | commitdiff |
2019-09-22 |
whitequark | hdl.rec: allow using Enum subclass as shape. |
tree | commitdiff |
2019-09-21 |
whitequark | hdl.ast: update docs. NFC. |
tree | commitdiff |
2019-09-20 |
whitequark | hdl.mem: use 1 as reset value for ReadPort.en. |
tree | commitdiff |
2019-09-20 |
whitequark | hdl.ast: rename `nbits` to `width`. |
tree | commitdiff |
2019-09-16 |
whitequark | hdl.{ast,dsl}: add Signal.enum; coerce Enum to Value... |
tree | commitdiff |
2019-09-14 |
whitequark | hdl.ast: add Value.matches(), accepting same language... |
tree | commitdiff |
2019-09-14 |
whitequark | hdl.dsl: improve error messages for Case(). |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.xor, mapping to $reduce_xor. |
tree | commitdiff |
2019-09-13 |
whitequark | hdl.ast: add Value.{any,all}, mapping to $reduce_{or... |
tree | commitdiff |
2019-09-12 |
whitequark | hdl.mem: use keyword-only arguments as appropriate. |
tree | commitdiff |
2019-09-10 |
whitequark | hdl.ast: warn if reset value is truncated. |
tree | commitdiff |
2019-09-08 |
whitequark | hdl.ast: check type of Sample(domain=...). |
tree | commitdiff |
2019-09-08 |
whitequark | hdl.dsl: add Default(), an alias for Case() with no... |
tree | commitdiff |
2019-09-08 |
whitequark | hdl.mem,lib,examples: use Signal.range(). |
tree | commitdiff |
2019-09-08 |
whitequark | hdl.ast: add Signal.range(...), to replace Signal(min... |
tree | commitdiff |
2019-09-03 |
whitequark | hdl.ast,back.rtlil: implement Cover. |
tree | commitdiff |
2019-08-31 |
whitequark | hdl.cd: add negedge clock domains. |
tree | commitdiff |
2019-08-19 |
whitequark | build.plat, hdl.ir: coordinate missing domain creation. |
tree | commitdiff |
2019-08-19 |
whitequark | hdl.cd: implement local clock domains. |
tree | commitdiff |
2019-08-19 |
whitequark | hdl.xfrm: lower resets in DomainLowerer as well. |
tree | commitdiff |
2019-08-19 |
whitequark | hdl.xfrm: consider fragment's own domains in DomainLowerer. |
tree | commitdiff |
2019-08-19 |
whitequark | formal→asserts |
tree | commitdiff |
2019-08-18 |
whitequark | hdl.xfrm: make deprecated CEInserter more well-behaved. |
tree | commitdiff |
2019-08-15 |
whitequark | hdl.ast: implement Initial. |
tree | commitdiff |
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