2019-01-16 |
whitequark | hdl.ast: fix naming of Signal.like() signals when trace... |
tree | commitdiff |
2019-01-15 |
William D. Jones | hdl.xfrm: Add on_AnyConst and on_AnySeq abstract method... |
tree | commitdiff |
2019-01-15 |
William D. Jones | hdl.ast: Add AnyConst and AnySeq value types. |
tree | commitdiff |
2019-01-14 |
whitequark | hdl.ir: allow explicitly requesting flattening. |
tree | commitdiff |
2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS. |
tree | commitdiff |
2019-01-13 |
whitequark | hdl.dsl: cases wider than switch test value are unreach... |
tree | commitdiff |
2019-01-13 |
whitequark | hdl.dsl: accept (but warn on) cases wider than switch... |
tree | commitdiff |
2019-01-02 |
whitequark | hdl.ast: allow slicing [n:n] into n-bit value. |
tree | commitdiff |
2019-01-02 |
William D. Jones | hdl.xfrm: Add Assert and Assume abstract methods for... |
tree | commitdiff |
2019-01-02 |
William D. Jones | hdl.dsl: Support Assert and Assume where an Assign... |
tree | commitdiff |
2019-01-02 |
William D. Jones | hdl.ast: Add Assert and Assign statements. |
tree | commitdiff |
2019-01-01 |
whitequark | hdl.ast: experimentally add Value._as_const. |
tree | commitdiff |
2019-01-01 |
whitequark | hdl.rec: include record name in error message. |
tree | commitdiff |
2019-01-01 |
whitequark | hdl.rec: use a helpful error on unknown field reference. |
tree | commitdiff |
2019-01-01 |
whitequark | hdl.mem: add DummyPort, for testing and verification. |
tree | commitdiff |
2018-12-29 |
whitequark | lib.cdc: fix tests to actually run. |
tree | commitdiff |
2018-12-28 |
whitequark | hdl.rec: add basic record support. |
tree | commitdiff |
2018-12-28 |
whitequark | tracer: factor out get_src_loc(). |
tree | commitdiff |
2018-12-27 |
whitequark | hdl.dsl: add support for fsm.ongoing(). |
tree | commitdiff |
2018-12-27 |
whitequark | hdl.mem: add missing __all__. |
tree | commitdiff |
2018-12-26 |
whitequark | hdl.dsl: forbid m.next= inside of FSM but outside of... |
tree | commitdiff |
2018-12-26 |
whitequark | hdl.dsl: provide generated values for FSMs. |
tree | commitdiff |
2018-12-26 |
whitequark | hdl.ir: add an API for retrieving generated values... |
tree | commitdiff |
2018-12-26 |
whitequark | examples: add an FSM usage example (UART receiver). |
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2018-12-26 |
whitequark | hdl.dsl: add signal decoder to FSM state signal. |
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2018-12-26 |
whitequark | hdl.dsl: implement FSM. |
tree | commitdiff |
2018-12-24 |
whitequark | hdl.mem: allow omitting memory simulation logic. |
tree | commitdiff |
2018-12-24 |
whitequark | hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. |
tree | commitdiff |
2018-12-24 |
whitequark | hdl.xfrm: implement SwitchCleaner, for pruning empty... |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.xfrm: avoid cycles in union-find graph in LHSGroupA... |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.ir: flatten hierarchy based on memory accesses... |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.ir: factor out _merge_subfragment. NFC. |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.xfrm: implement LHSGroupAnalyzer. |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.xfrm: Abstract*Transformer→*Visitor |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.mem: allow changing init value after creating memory. |
tree | commitdiff |
2018-12-22 |
whitequark | hdl.ir: fix port propagation between siblings, in the... |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: use more informative signal naming for ports. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.ir: fix port propagation between siblings. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.ir: do not flatten instances or collect ports from... |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: ensure transparent read port model has correct... |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: use different naming for array signals. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: add simulation model for memory. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: add tests for all error conditions. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: tie rdport.en high for asynchronous or transpa... |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.ir: correctly handle named output and inout ports. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: implement memories. |
tree | commitdiff |
2018-12-20 |
whitequark | ir: allow non-Signals in Instance ports. |
tree | commitdiff |
2018-12-18 |
whitequark | compat: import genlib.record from Migen. |
tree | commitdiff |
2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts} |
tree | commitdiff |
2018-12-18 |
whitequark | hdl.ast, hdl.xfrm: various microoptimizations to speed... |
tree | commitdiff |
2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters... |
tree | commitdiff |
2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict. |
tree | commitdiff |
2018-12-17 |
whitequark | hdl.ast: factor out _MappedKeyDict, _MappedKeySet.... |
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2018-12-17 |
whitequark | back.rtlil: implement Array. |
tree | commitdiff |
2018-12-17 |
whitequark | back.rtlil: implement Part. |
tree | commitdiff |
2018-12-16 |
whitequark | hdl.dsl: add clock domain support. |
tree | commitdiff |
2018-12-16 |
whitequark | hdl.dsl: cleanup. NFC. |
tree | commitdiff |
2018-12-16 |
whitequark | hdl.xfrm: separate AST traversal from AST identity... |
tree | commitdiff |
2018-12-16 |
whitequark | compat.fhdl: reexport Array. |
tree | commitdiff |
2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: implement Part. |
tree | commitdiff |
2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | hdl.ast: implement Array and ArrayProxy. |
tree | commitdiff |
2018-12-15 |
whitequark | hdl.ast: improve ClockSignal, ResetSignal documentation. |
tree | commitdiff |
2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
tree | commitdiff |
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