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hdl.ast: allow sampling ClockSignal, ResetSignal.
[nmigen.git] / nmigen / hdl /
2019-01-17 whitequarkhdl.ast: allow sampling ClockSignal, ResetSignal. tree | commitdiff
2019-01-17 whitequarkhdl.ast: add Past, Stable, Rose, Fell. tree | commitdiff
2019-01-17 whitequarkhdl.xfrm: add SampleLowerer. tree | commitdiff
2019-01-17 whitequarkhdl.ast: add Sample. tree | commitdiff
2019-01-16 whitequarkhdl.ast: fix naming of Signal.like() signals when trace... tree | commitdiff
2019-01-15 William D. Joneshdl.xfrm: Add on_AnyConst and on_AnySeq abstract method... tree | commitdiff
2019-01-15 William D. Joneshdl.ast: Add AnyConst and AnySeq value types. tree | commitdiff
2019-01-14 whitequarkhdl.ir: allow explicitly requesting flattening. tree | commitdiff
2019-01-14 whitequarkhdl: make ClockSignal and ResetSignal usable on LHS. tree | commitdiff
2019-01-13 whitequarkhdl.dsl: cases wider than switch test value are unreach... tree | commitdiff
2019-01-13 whitequarkhdl.dsl: accept (but warn on) cases wider than switch... tree | commitdiff
2019-01-02 whitequarkhdl.ast: allow slicing [n:n] into n-bit value. tree | commitdiff
2019-01-02 William D. Joneshdl.xfrm: Add Assert and Assume abstract methods for... tree | commitdiff
2019-01-02 William D. Joneshdl.dsl: Support Assert and Assume where an Assign... tree | commitdiff
2019-01-02 William D. Joneshdl.ast: Add Assert and Assign statements. tree | commitdiff
2019-01-01 whitequarkhdl.ast: experimentally add Value._as_const. tree | commitdiff
2019-01-01 whitequarkhdl.rec: include record name in error message. tree | commitdiff
2019-01-01 whitequarkhdl.rec: use a helpful error on unknown field reference. tree | commitdiff
2019-01-01 whitequarkhdl.mem: add DummyPort, for testing and verification. tree | commitdiff
2018-12-29 whitequarklib.cdc: fix tests to actually run. tree | commitdiff
2018-12-28 whitequarkhdl.rec: add basic record support. tree | commitdiff
2018-12-28 whitequarktracer: factor out get_src_loc(). tree | commitdiff
2018-12-27 whitequarkhdl.dsl: add support for fsm.ongoing(). tree | commitdiff
2018-12-27 whitequarkhdl.mem: add missing __all__. tree | commitdiff
2018-12-26 whitequarkhdl.dsl: forbid m.next= inside of FSM but outside of... tree | commitdiff
2018-12-26 whitequarkhdl.dsl: provide generated values for FSMs. tree | commitdiff
2018-12-26 whitequarkhdl.ir: add an API for retrieving generated values... tree | commitdiff
2018-12-26 whitequarkexamples: add an FSM usage example (UART receiver). tree | commitdiff
2018-12-26 whitequarkhdl.dsl: add signal decoder to FSM state signal. tree | commitdiff
2018-12-26 whitequarkhdl.dsl: implement FSM. tree | commitdiff
2018-12-24 whitequarkhdl.mem: allow omitting memory simulation logic. tree | commitdiff
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter. tree | commitdiff
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty... tree | commitdiff
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA... tree | commitdiff
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses... tree | commitdiff
2018-12-22 whitequarkhdl.ir: factor out _merge_subfragment. NFC. tree | commitdiff
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer. tree | commitdiff
2018-12-22 whitequarkhdl.xfrm: Abstract*Transformer→*Visitor tree | commitdiff
2018-12-22 whitequarkhdl.mem: allow changing init value after creating memory. tree | commitdiff
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the... tree | commitdiff
2018-12-21 whitequarkhdl.mem: use more informative signal naming for ports. tree | commitdiff
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings. tree | commitdiff
2018-12-21 whitequarkhdl.ir: do not flatten instances or collect ports from... tree | commitdiff
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct... tree | commitdiff
2018-12-21 whitequarkhdl.mem: use different naming for array signals. tree | commitdiff
2018-12-21 whitequarkhdl.mem: add simulation model for memory. tree | commitdiff
2018-12-21 whitequarkhdl.mem: add tests for all error conditions. tree | commitdiff
2018-12-21 whitequarkhdl.mem: tie rdport.en high for asynchronous or transpa... tree | commitdiff
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports. tree | commitdiff
2018-12-21 whitequarkhdl.mem: implement memories. tree | commitdiff
2018-12-20 whitequarkir: allow non-Signals in Instance ports. tree | commitdiff
2018-12-18 whitequarkcompat: import genlib.record from Migen. tree | commitdiff
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts} tree | commitdiff
2018-12-18 whitequarkhdl.ast, hdl.xfrm: various microoptimizations to speed... tree | commitdiff
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters... tree | commitdiff
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict. tree | commitdiff
2018-12-17 whitequarkhdl.ast: factor out _MappedKeyDict, _MappedKeySet.... tree | commitdiff
2018-12-17 whitequarkback.rtlil: implement Array. tree | commitdiff
2018-12-17 whitequarkback.rtlil: implement Part. tree | commitdiff
2018-12-16 whitequarkhdl.dsl: add clock domain support. tree | commitdiff
2018-12-16 whitequarkhdl.dsl: cleanup. NFC. tree | commitdiff
2018-12-16 whitequarkhdl.xfrm: separate AST traversal from AST identity... tree | commitdiff
2018-12-16 whitequarkcompat.fhdl: reexport Array. tree | commitdiff
2018-12-16 whitequarkback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. tree | commitdiff
2018-12-15 whitequarkback.pysim: implement Part. tree | commitdiff
2018-12-15 whitequarkback.pysim: implement ArrayProxy. tree | commitdiff
2018-12-15 whitequarkhdl.ast: implement Array and ArrayProxy. tree | commitdiff
2018-12-15 whitequarkhdl.ast: improve ClockSignal, ResetSignal documentation. tree | commitdiff
2018-12-15 whitequarkRename fhdl→hdl, genlib→lib. tree | commitdiff