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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
[nmigen.git]
/
nmigen
/
test
/
__init__.py
2019-04-21
whitequark
hdl.ir: detect elaboratables that are created but not...
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2018-12-13
whitequark
fhdl.ast: add tests for most logic.
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