hdl.mem: use read_port(domain="comb") for asynchronous read ports.
[nmigen.git] / nmigen / test / test_build_dsl.py
2019-06-12 whitequarkbuild.{dsl,res,plat}: add PinsN and DiffPairsN.
2019-06-05 whitequarkbuild.{dsl,res,plat}: apply clock constraints to signal...
2019-06-05 whitequarkbuild.dsl: replace extras= with Attrs().
2019-06-03 whitequarkbuild.dsl: add support for connectors.
2019-06-03 whitequarkbuild.{dsl,plat,res}: allow dir="oe".
2019-06-02 whitequarkbuild.dsl: require a dict for extras instead of a strin...
2019-05-25 whitequarkbuild.dsl: make Pins and DiffPairs iterable.
2019-05-25 whitequarkbuild.dsl: improve repr of Pins() and DiffPairs().
2019-04-24 Jean-François Nguyenbuild: add DSL for defining platform resources.