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hdl.mem: use read_port(domain="comb") for asynchronous read ports.
[nmigen.git]
/
nmigen
/
test
/
test_build_dsl.py
2019-06-12
whitequark
build.{dsl,res,plat}: add PinsN and DiffPairsN.
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2019-06-05
whitequark
build.{dsl,res,plat}: apply clock constraints to signal...
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2019-06-05
whitequark
build.dsl: replace extras= with Attrs().
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2019-06-03
whitequark
build.dsl: add support for connectors.
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2019-06-03
whitequark
build.{dsl,plat,res}: allow dir="oe".
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2019-06-02
whitequark
build.dsl: require a dict for extras instead of a strin...
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2019-05-25
whitequark
build.dsl: make Pins and DiffPairs iterable.
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2019-05-25
whitequark
build.dsl: improve repr of Pins() and DiffPairs().
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2019-04-24
Jean-François Nguyen
build: add DSL for defining platform resources.
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