hdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case values.
[nmigen.git] / nmigen / test / test_lib_fifo.py
2019-06-04 whitequarkClean up imports.
2019-04-21 whitequarkhdl.ir: detect elaboratables that are created but not...
2019-01-26 whitequarkhdl.ir: rename .get_fragment() to .elaborate().
2019-01-21 whitequarklib.fifo: add AsyncFIFO and AsyncFIFOBuffered.
2019-01-19 whitequarklib.fifo: use memory in the FIFO model.
2019-01-19 whitequarklib.fifo: use model equivalence to simplify formal...
2019-01-19 whitequarkhdl.xfrm: mark internal registers used in lowering...
2019-01-19 whitequarklib.fifo: formally verify FIFO contract.
2019-01-17 whitequarklib.fifo: add basic formal specification.
2019-01-16 whitequarklib.fifo: port sync FIFO queues from Migen.