| 2019-08-03 |
whitequark | hdl.ast: deprecate Value.part, add Value.{bit,word... |
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| 2019-07-01 |
whitequark | hdl.mem: use read_port(domain="comb") for asynchronous... |
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| 2019-06-11 |
whitequark | back.pysim: check for a clock being added twice. |
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| 2019-03-28 |
whitequark | test_sim: add missing add_process(). |
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| 2019-01-26 |
whitequark | hdl.ir: rename .get_fragment() to .elaborate(). |
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| 2019-01-25 |
whitequark | back.pysim: fix behavior of initial cycle for sync... |
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| 2019-01-21 |
whitequark | back.pysim: wake up processes before ever committing... |
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| 2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell. |
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| 2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals. |
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| 2018-12-29 |
whitequark | back.pysim: warn if simulation is not run. |
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| 2018-12-28 |
whitequark | hdl.rec: add basic record support. |
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| 2018-12-21 |
whitequark | hdl.mem: ensure transparent read port model has correct... |
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| 2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
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| 2018-12-21 |
whitequark | hdl.mem: add simulation model for memory. |
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| 2018-12-18 |
whitequark | back.pysim: implement *. |
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| 2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors. |
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| 2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
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| 2018-12-15 |
whitequark | test.sim: generalize assertOperator. NFC. |
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| 2018-12-15 |
whitequark | back.pysim: implement Part. |
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| 2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
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| 2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
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| 2018-12-15 |
whitequark | pyback.sim: test Slice, Cat, Repl. |
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| 2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
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| 2018-12-14 |
whitequark | fhdl.ir: Fragment.{drive→add_driver} |
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| 2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
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| 2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
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projects / nmigen.git / history