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back.pysim: fix miscompilation of Signal(unsigned) - Signal(signed).
[nmigen.git] / nmigen / test /
2019-11-28 whitequarkback.pysim: redesign the simulator. tree | commitdiff
2019-11-26 whitequarkhdl.ir: for instance ports, prioritize defs over uses. tree | commitdiff
2019-11-15 whitequarkbuild.plat: in Platform.add_file(), allow adding exact... tree | commitdiff
2019-11-15 whitequarktest: add tests for build.plat.Platform.add_file. tree | commitdiff
2019-11-07 whitequarkhdl.ir: lower domains before resolving hierarchy conflicts. tree | commitdiff
2019-10-26 whitequarktest: use `#nmigen:` magic comment instead of monkey... tree | commitdiff
2019-10-26 whitequarkhdl.ast: simplify {bit,word}_select with constant offset. tree | commitdiff
2019-10-13 whitequark{,_}tools→{,_}utils tree | commitdiff
2019-10-13 whitequarkhdl.ir: allow ClockSignal and ResetSignal in ports. tree | commitdiff
2019-10-13 whitequarkhdl.ir: cast instance port connections to Values. tree | commitdiff
2019-10-12 whitequarkhdl.ast: rename Slice.end back to Slice.stop. tree | commitdiff
2019-10-12 whitequark_tools: extract most utility methods to a private package. tree | commitdiff
2019-10-11 whitequarkRename remaining `wrap` methods to `cast`. tree | commitdiff
2019-10-11 whitequarkhdl.ast: deprecate shapes like `(1, True)` in favor... tree | commitdiff
2019-10-11 whitequarkhdl.ast: deprecate Signal.{range,enum}. tree | commitdiff
2019-10-11 whitequarkhdl.ast: add an explicit Shape class, included in prelude. tree | commitdiff
2019-10-11 whitequarkConsistently use {!r}, not '{!r}' in diagnostics. tree | commitdiff
2019-10-11 whitequarkhdl.ast: simplify enum handling. tree | commitdiff
2019-10-11 whitequarkhdl.ast: Value.{wrap→cast} tree | commitdiff
2019-10-04 whitequarkhdl.ast: prohibit signed divisors. tree | commitdiff
2019-10-03 whitequarkbuild.dsl: accept Pins(invert=True). tree | commitdiff
2019-10-02 whitequarkhdl.ast: don't crash on Mux(<bool>, ...). tree | commitdiff
2019-09-28 whitequarkhdl.ast: actually implement the // operator. tree | commitdiff
2019-09-28 whitequarkhdl.dsl: add a diagnostic for `m.d.submodules += ...`. tree | commitdiff
2019-09-28 whitequarkhdl.mem: remove WritePort(priority=) argument. tree | commitdiff
2019-09-23 whitequarklib.cdc: add diagnostic checks for synchronization... tree | commitdiff
2019-09-23 whitequarklib.cdc: MultiReg→FFSynchronizer. tree | commitdiff
2019-09-23 whitequarkhdl.ast: cast Mux() selector to bool if it is not a... tree | commitdiff
2019-09-23 whitequarklib.fifo: handle depth=0, elaborating to a dummy FIFO... tree | commitdiff
2019-09-23 whitequarkhdl.mem,lib.fifo: use keyword-only arguments for memory... tree | commitdiff
2019-09-23 whitequarkhdl.mem: simplify. NFC. tree | commitdiff
2019-09-23 whitequarkhdl.ast: make Signal(name=) a keyword-only argument. tree | commitdiff
2019-09-23 whitequarklib.fifo: change FIFOInterface() diagnostics to follow... tree | commitdiff
2019-09-23 whitequarklib.fifo: round up AsyncFIFO{,Buffered} depth to lowest... tree | commitdiff
2019-09-23 whitequarklib.fifo: make simulation read() and write() functions... tree | commitdiff
2019-09-22 whitequarkhdl.rec: fix using Enum subclass as shape if direction... tree | commitdiff
2019-09-22 whitequarkhdl.rec: allow using Enum subclass as shape. tree | commitdiff
2019-09-21 whitequarkbuild.res: simplify clock constraints. tree | commitdiff
2019-09-20 whitequarkhdl.mem: use 1 as reset value for ReadPort.en. tree | commitdiff
2019-09-20 whitequarkhdl.ast: rename `nbits` to `width`. tree | commitdiff
2019-09-20 whitequarktest.test_lib_fifo: fix typo. tree | commitdiff
2019-09-20 whitequarkback.pysim: fix simulation of Value.xor(). tree | commitdiff
2019-09-16 whitequarkhdl.{ast,dsl}: add Signal.enum; coerce Enum to Value... tree | commitdiff
2019-09-14 whitequarkhdl.ast: add Value.matches(), accepting same language... tree | commitdiff
2019-09-14 whitequarkhdl.dsl: improve error messages for Case(). tree | commitdiff
2019-09-13 whitequarkhdl.ast: add Value.xor, mapping to $reduce_xor. tree | commitdiff
2019-09-13 whitequarkhdl.ast: add Value.{any,all}, mapping to $reduce_{or... tree | commitdiff
2019-09-13 whitequarklib.fifo: adjust properties to have consistent naming. tree | commitdiff
2019-09-12 whitequarklib.fifo: make fwft a keyword-only argument. tree | commitdiff
2019-09-12 whitequarklib.fifo: remove SyncFIFO.replace. tree | commitdiff
2019-09-10 whitequarkhdl.ast: warn if reset value is truncated. tree | commitdiff
2019-09-08 whitequarkhdl.ast: check type of Sample(domain=...). tree | commitdiff
2019-09-08 whitequarkhdl.dsl: add Default(), an alias for Case() with no... tree | commitdiff
2019-09-08 whitequarkhdl.mem,lib,examples: use Signal.range(). tree | commitdiff
2019-09-08 whitequarkhdl.ast: add Signal.range(...), to replace Signal(min... tree | commitdiff
2019-09-03 whitequarkhdl.ast,back.rtlil: implement Cover. tree | commitdiff
2019-08-31 whitequarkhdl.cd: add negedge clock domains. tree | commitdiff
2019-08-31 Emily_toolchain,build.plat,vendor.*: add required_tools... tree | commitdiff
2019-08-30 whitequarkbuild.dsl: allow both str and int resource attributes. tree | commitdiff
2019-08-28 Emilytest.tools: use _toolchain.get_tool. tree | commitdiff
2019-08-23 whitequarkback.pysim: implement sim.add_clock(if_exists=True). locally_working tree | commitdiff
2019-08-23 whitequarkback.pysim: don't crash when trying to drive a nonexist... tree | commitdiff
2019-08-20 William D. Jonestest.test_examples: Convert pathlib-specific class... tree | commitdiff
2019-08-19 whitequarkbuild.plat, hdl.ir: coordinate missing domain creation. tree | commitdiff
2019-08-19 whitequarkhdl.cd: implement local clock domains. tree | commitdiff
2019-08-19 whitequarkhdl.xfrm: lower resets in DomainLowerer as well. tree | commitdiff
2019-08-19 whitequarkhdl.xfrm: consider fragment's own domains in DomainLowerer. tree | commitdiff
2019-08-19 whitequarkformal→asserts tree | commitdiff
2019-08-18 Robin Heinemannbuild.dsl: add conn argument to Connector. tree | commitdiff
2019-08-15 whitequarkhdl.ast: implement Initial. tree | commitdiff
2019-08-12 whitequarkhdl.xfrm: CEInserter→EnableInserter. tree | commitdiff
2019-08-03 whitequarkhdl.dsl: reword m.If(~True) warning to be more clear. tree | commitdiff
2019-08-03 whitequarkhdl.ir: allow adding more than one domain in missing... tree | commitdiff
2019-08-03 whitequarkhdl.ir: don't expose as ports missing domains added... tree | commitdiff
2019-08-03 whitequarkhdl.ir: allow returning elaboratables from missing... tree | commitdiff
2019-08-03 whitequarkhdl.ir: raise DomainError if a domain is used but not... tree | commitdiff
2019-08-03 whitequarkhdl.ir: call back from Fragment.prepare if a clock... tree | commitdiff
2019-08-03 whitequarkhdl.dsl: warn on suspicious statements like `m.If(... tree | commitdiff
2019-08-03 whitequarkImprove test added in 29fee01f to not leak warnings. tree | commitdiff
2019-08-03 whitequarkhdl.ast: deprecate Value.part, add Value.{bit,word... tree | commitdiff
2019-08-03 whitequarkhdl.ir: warn if .elaborate() returns None. tree | commitdiff
2019-07-31 whitequarkhdl.xfrm: handle mem.{Read,Write}Port in CEInserter. tree | commitdiff
2019-07-19 N. Engelhardthdl.dsl: add getters to m.submodules. tree | commitdiff
2019-07-10 William D. Jonesbuild.dsl: Add optional name_suffix to Resource.family. tree | commitdiff
2019-07-09 whitequarkbuild.dsl: add Resource.family abstraction. tree | commitdiff
2019-07-08 whitequarkbuild.{dsl,res}: allow platform-dependent attributes... tree | commitdiff
2019-07-08 whitequarkhdl.rec: respect modifications to signals in Record... tree | commitdiff
2019-07-08 whitequarkbuild.{dsl,res}: allow removing attributes from subsignals. tree | commitdiff
2019-07-08 whitequarkbuild.dsl: allow assertions on subsignal widths. tree | commitdiff
2019-07-08 whitequarkhdl.{ast,cd,dsl,xfrm}: reject inappropriately used... tree | commitdiff
2019-07-08 whitequarktest: generate examples to verilog as part of unit... tree | commitdiff
2019-07-07 whitequarkhdl.dsl: further clarify error message for incorrect... tree | commitdiff
2019-07-07 whitequarkhdl.dsl: clarify error message for incorrect nesting. tree | commitdiff
2019-07-07 whitequarkhdl.dsl: gracefully handle FSM with no states. tree | commitdiff
2019-07-03 whitequarkbuild.res: detect physical conflicts earlier. tree | commitdiff
2019-07-02 whitequarkhdl.ast: recognize a Enum used as decoder and format... tree | commitdiff
2019-07-02 whitequarkhdl.rec: implement slicing by component names. tree | commitdiff
2019-07-02 whitequarkhdl.rec: implement Record.like. tree | commitdiff
2019-07-01 whitequarkhdl.mem: use read_port(domain="comb") for asynchronous... tree | commitdiff
2019-06-28 whitequarkhdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case... tree | commitdiff
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