2019-01-20 |
whitequark | lib.coding: add GrayEncoder and GrayDecoder. |
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2019-01-19 |
whitequark | lib.fifo: use memory in the FIFO model. |
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2019-01-19 |
whitequark | lib.fifo: use model equivalence to simplify formal... |
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2019-01-19 |
whitequark | hdl.xfrm: mark internal registers used in lowering... |
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2019-01-19 |
whitequark | lib.fifo: formally verify FIFO contract. |
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2019-01-17 |
whitequark | lib.fifo: add basic formal specification. |
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2019-01-17 |
whitequark | hdl.ast: allow sampling ClockSignal, ResetSignal. |
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2019-01-17 |
whitequark | hdl.ast: add Past, Stable, Rose, Fell. |
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2019-01-17 |
whitequark | hdl.xfrm: add SampleLowerer. |
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2019-01-17 |
whitequark | hdl.ast: add Sample. |
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2019-01-16 |
whitequark | lib.fifo: port sync FIFO queues from Migen. |
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2019-01-16 |
whitequark | hdl.ast: fix naming of Signal.like() signals when trace... |
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2019-01-14 |
whitequark | hdl.ir: allow explicitly requesting flattening. |
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2019-01-14 |
whitequark | hdl: make ClockSignal and ResetSignal usable on LHS. |
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2019-01-13 |
whitequark | hdl.dsl: cases wider than switch test value are unreach... |
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2019-01-13 |
whitequark | hdl.dsl: accept (but warn on) cases wider than switch... |
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2019-01-13 |
whitequark | back.pysim: handle non-driven, non-port signals. |
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2019-01-02 |
William D. Jones | hdl.dsl: Support Assert and Assume where an Assign... |
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2019-01-01 |
whitequark | hdl.rec: include record name in error message. |
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2019-01-01 |
whitequark | hdl.rec: use a helpful error on unknown field reference. |
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2019-01-01 |
whitequark | hdl.mem: add DummyPort, for testing and verification. |
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2018-12-29 |
whitequark | lib.cdc: fix tests to actually run. |
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2018-12-29 |
whitequark | back.pysim: warn if simulation is not run. |
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2018-12-28 |
whitequark | hdl.rec: add basic record support. |
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2018-12-27 |
whitequark | lib.coding: fix tests to actually run, and fix code... |
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2018-12-27 |
whitequark | hdl.dsl: add support for fsm.ongoing(). |
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2018-12-26 |
whitequark | lib.coding: port from Migen. |
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2018-12-26 |
whitequark | lib.cdc: add tests for MultiReg. |
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2018-12-26 |
whitequark | hdl.dsl: forbid m.next= inside of FSM but outside of... |
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2018-12-26 |
whitequark | hdl.dsl: provide generated values for FSMs. |
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2018-12-26 |
whitequark | hdl.ir: add an API for retrieving generated values... |
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2018-12-26 |
whitequark | hdl.dsl: implement FSM. |
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2018-12-24 |
whitequark | hdl.xfrm, back.rtlil: implement and use LHSGroupFilter. |
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2018-12-24 |
whitequark | hdl.xfrm: implement SwitchCleaner, for pruning empty... |
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2018-12-22 |
whitequark | hdl.xfrm: avoid cycles in union-find graph in LHSGroupA... |
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2018-12-22 |
whitequark | hdl.ir: flatten hierarchy based on memory accesses... |
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2018-12-22 |
whitequark | hdl.xfrm: implement LHSGroupAnalyzer. |
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2018-12-22 |
whitequark | hdl.ir: fix port propagation between siblings, in the... |
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2018-12-21 |
whitequark | hdl.ir: fix port propagation between siblings. |
tree | commitdiff |
2018-12-21 |
whitequark | hdl.mem: ensure transparent read port model has correct... |
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2018-12-21 |
whitequark | back.pysim: handle out of bounds ArrayProxy indexes. |
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2018-12-21 |
whitequark | hdl.mem: add simulation model for memory. |
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2018-12-21 |
whitequark | hdl.mem: add tests for all error conditions. |
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2018-12-21 |
whitequark | hdl.ir: correctly handle named output and inout ports. |
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2018-12-20 |
whitequark | ir: allow non-Signals in Instance ports. |
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2018-12-18 |
whitequark | hdl.ast: Cat.{operands→parts} |
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2018-12-18 |
whitequark | back.pysim: implement *. |
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2018-12-18 |
whitequark | test.sim: add tests for sync functionality and errors. |
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2018-12-17 |
whitequark | fhdl.ir: add black-box fragments, fragment parameters... |
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2018-12-17 |
whitequark | hdl, back: add and use SignalSet/SignalDict. |
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2018-12-16 |
whitequark | hdl.dsl: add clock domain support. |
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2018-12-16 |
whitequark | back.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. |
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2018-12-15 |
whitequark | test.sim: generalize assertOperator. NFC. |
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2018-12-15 |
whitequark | back.pysim: implement Part. |
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2018-12-15 |
whitequark | back.pysim: implement ArrayProxy. |
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2018-12-15 |
whitequark | hdl.ast: implement Array and ArrayProxy. |
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2018-12-15 |
whitequark | hdl: appropriately rename tests. NFC. |
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2018-12-15 |
whitequark | Rename fhdl→hdl, genlib→lib. |
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2018-12-15 |
whitequark | pyback.sim: test Slice, Cat, Repl. |
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2018-12-15 |
whitequark | fhdl.ast, back.pysim: implement shifts. |
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2018-12-15 |
whitequark | fhdl.ast: refactor Operator.shape(). NFC. |
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2018-12-15 |
whitequark | fhdl.ir: test iter_comb(), iter_sync() and iter_signals(). |
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2018-12-15 |
whitequark | fhdl.ir: fix incorrect uses of positive to say non... |
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2018-12-14 |
whitequark | fhdl.ir: automatically flatten hierarchy to resolve... |
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2018-12-14 |
whitequark | fhdl.ir: Fragment.{drive→add_driver} |
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2018-12-14 |
whitequark | fhdl.ast: fix Switch with constant test. |
tree | commitdiff |
2018-12-14 |
whitequark | back.pysim: Simulator({gtkw_signals→traces}=). |
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2018-12-14 |
whitequark | back.pysim: implement most operators and add tests. |
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2018-12-14 |
whitequark | fhdl.xfrm: implement DomainLowerer. |
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2018-12-13 |
whitequark | back.pysim: new simulator backend (WIP). |
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2018-12-13 |
whitequark | fhdl.cd: rename ClockDomain signals together with domain. |
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2018-12-13 |
whitequark | fhdl.ir: move Fragment prepare logic from back.rtlil. |
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2018-12-13 |
whitequark | fhdl.ir: record port direction explicitly. |
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2018-12-13 |
whitequark | fhdl.ir: a subfragment's input that we don't drive... |
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2018-12-13 |
whitequark | fhdl.ir: don't crash propagataing ports in empty fragments. |
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2018-12-13 |
whitequark | fhdl.ir: implement clock domain propagation. |
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2018-12-13 |
whitequark | fhdl.cd: add tests. |
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2018-12-13 |
whitequark | fhdl.xfrm: implement DomainRenamer. |
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2018-12-13 |
whitequark | fhdl.xfrm: add test for ControlInserter with subfragments. |
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2018-12-13 |
whitequark | fhdl.xfrm: add tests for ResetInserter, CEInserter. |
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2018-12-13 |
whitequark | fhdl.ir: add tests for port propagation. |
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2018-12-13 |
whitequark | fhdl.dsl: add tests for lowering. 99% branch coverage. |
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2018-12-13 |
whitequark | fhdl.dsl: add tests for submodules. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.dsl: use less error-prone Switch/Case two-level... |
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2018-12-13 |
whitequark | fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. |
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2018-12-13 |
whitequark | fhdl.ast: bits_sign→shape. |
tree | commitdiff |
2018-12-13 |
whitequark | fhdl.ast: add tests for most logic. |
tree | commitdiff |
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