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lib.cdc: add tests for MultiReg.
[nmigen.git] / nmigen / test /
2018-12-26 whitequarklib.cdc: add tests for MultiReg. tree | commitdiff
2018-12-26 whitequarkhdl.dsl: forbid m.next= inside of FSM but outside of... tree | commitdiff
2018-12-26 whitequarkhdl.dsl: provide generated values for FSMs. tree | commitdiff
2018-12-26 whitequarkhdl.ir: add an API for retrieving generated values... tree | commitdiff
2018-12-26 whitequarkhdl.dsl: implement FSM. tree | commitdiff
2018-12-24 whitequarkhdl.xfrm, back.rtlil: implement and use LHSGroupFilter. tree | commitdiff
2018-12-24 whitequarkhdl.xfrm: implement SwitchCleaner, for pruning empty... tree | commitdiff
2018-12-22 whitequarkhdl.xfrm: avoid cycles in union-find graph in LHSGroupA... tree | commitdiff
2018-12-22 whitequarkhdl.ir: flatten hierarchy based on memory accesses... tree | commitdiff
2018-12-22 whitequarkhdl.xfrm: implement LHSGroupAnalyzer. tree | commitdiff
2018-12-22 whitequarkhdl.ir: fix port propagation between siblings, in the... tree | commitdiff
2018-12-21 whitequarkhdl.ir: fix port propagation between siblings. tree | commitdiff
2018-12-21 whitequarkhdl.mem: ensure transparent read port model has correct... tree | commitdiff
2018-12-21 whitequarkback.pysim: handle out of bounds ArrayProxy indexes. tree | commitdiff
2018-12-21 whitequarkhdl.mem: add simulation model for memory. tree | commitdiff
2018-12-21 whitequarkhdl.mem: add tests for all error conditions. tree | commitdiff
2018-12-21 whitequarkhdl.ir: correctly handle named output and inout ports. tree | commitdiff
2018-12-20 whitequarkir: allow non-Signals in Instance ports. tree | commitdiff
2018-12-18 whitequarkhdl.ast: Cat.{operands→parts} tree | commitdiff
2018-12-18 whitequarkback.pysim: implement *. tree | commitdiff
2018-12-18 whitequarktest.sim: add tests for sync functionality and errors. tree | commitdiff
2018-12-17 whitequarkfhdl.ir: add black-box fragments, fragment parameters... tree | commitdiff
2018-12-17 whitequarkhdl, back: add and use SignalSet/SignalDict. tree | commitdiff
2018-12-16 whitequarkhdl.dsl: add clock domain support. tree | commitdiff
2018-12-16 whitequarkback.pysim: implement LHS for Part, Slice, Cat, ArrayProxy. tree | commitdiff
2018-12-15 whitequarktest.sim: generalize assertOperator. NFC. tree | commitdiff
2018-12-15 whitequarkback.pysim: implement Part. tree | commitdiff
2018-12-15 whitequarkback.pysim: implement ArrayProxy. tree | commitdiff
2018-12-15 whitequarkhdl.ast: implement Array and ArrayProxy. tree | commitdiff
2018-12-15 whitequarkhdl: appropriately rename tests. NFC. tree | commitdiff
2018-12-15 whitequarkRename fhdl→hdl, genlib→lib. tree | commitdiff
2018-12-15 whitequarkpyback.sim: test Slice, Cat, Repl. tree | commitdiff
2018-12-15 whitequarkfhdl.ast, back.pysim: implement shifts. tree | commitdiff
2018-12-15 whitequarkfhdl.ast: refactor Operator.shape(). NFC. tree | commitdiff
2018-12-15 whitequarkfhdl.ir: test iter_comb(), iter_sync() and iter_signals(). tree | commitdiff
2018-12-15 whitequarkfhdl.ir: fix incorrect uses of positive to say non... tree | commitdiff
2018-12-14 whitequarkfhdl.ir: automatically flatten hierarchy to resolve... tree | commitdiff
2018-12-14 whitequarkfhdl.ir: Fragment.{drive→add_driver} tree | commitdiff
2018-12-14 whitequarkfhdl.ast: fix Switch with constant test. tree | commitdiff
2018-12-14 whitequarkback.pysim: Simulator({gtkw_signals→traces}=). tree | commitdiff
2018-12-14 whitequarkback.pysim: implement most operators and add tests. tree | commitdiff
2018-12-14 whitequarkfhdl.xfrm: implement DomainLowerer. tree | commitdiff
2018-12-13 whitequarkback.pysim: new simulator backend (WIP). tree | commitdiff
2018-12-13 whitequarkfhdl.cd: rename ClockDomain signals together with domain. tree | commitdiff
2018-12-13 whitequarkfhdl.ir: move Fragment prepare logic from back.rtlil. tree | commitdiff
2018-12-13 whitequarkfhdl.ir: record port direction explicitly. tree | commitdiff
2018-12-13 whitequarkfhdl.ir: a subfragment's input that we don't drive... tree | commitdiff
2018-12-13 whitequarkfhdl.ir: don't crash propagataing ports in empty fragments. tree | commitdiff
2018-12-13 whitequarkfhdl.ir: implement clock domain propagation. tree | commitdiff
2018-12-13 whitequarkfhdl.cd: add tests. tree | commitdiff
2018-12-13 whitequarkfhdl.xfrm: implement DomainRenamer. tree | commitdiff
2018-12-13 whitequarkfhdl.xfrm: add test for ControlInserter with subfragments. tree | commitdiff
2018-12-13 whitequarkfhdl.xfrm: add tests for ResetInserter, CEInserter. tree | commitdiff
2018-12-13 whitequarkfhdl.ir: add tests for port propagation. tree | commitdiff
2018-12-13 whitequarkfhdl.dsl: add tests for lowering. 99% branch coverage. tree | commitdiff
2018-12-13 whitequarkfhdl.dsl: add tests for submodules. tree | commitdiff
2018-12-13 whitequarkfhdl.dsl: use less error-prone Switch/Case two-level... tree | commitdiff
2018-12-13 whitequarkfhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else. tree | commitdiff
2018-12-13 whitequarkfhdl.ast: bits_sign→shape. tree | commitdiff
2018-12-13 whitequarkfhdl.ast: add tests for most logic. tree | commitdiff