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back.pysim: correctly add gtkwave traces for signals with decoders.
[nmigen.git] / nmigen /
2019-07-12 whitequarkback.pysim: correctly add gtkwave traces for signals... tree | commitdiff
2019-07-10 William D. Jonesbuild.dsl: Add optional name_suffix to Resource.family. tree | commitdiff
2019-07-10 whitequarkback.pysim: avoid malformed VCD files when a decoder... tree | commitdiff
2019-07-10 whitequarkhdl.ir: make UnusedElaboratable a real warning. tree | commitdiff
2019-07-09 whitequarkback.rtlil: add decodings to cases when switching on... tree | commitdiff
2019-07-09 whitequarkback.verilog: run proc_prune for much cleaner output. tree | commitdiff
2019-07-09 whitequarkhdl.{ast,dsl},back.rtlil: track source locations for... tree | commitdiff
2019-07-09 Jacob Lifshaytracer: add PyPy support to get_var_name(). tree | commitdiff
2019-07-09 whitequarkbuild.dsl: add Resource.family abstraction. tree | commitdiff
2019-07-08 whitequarkbuild.{dsl,res}: allow platform-dependent attributes... tree | commitdiff
2019-07-08 whitequarkhdl.rec: respect modifications to signals in Record... tree | commitdiff
2019-07-08 whitequarkback.rtlil: don't name-prefix signals connected to... tree | commitdiff
2019-07-08 whitequarkbuild.{dsl,res}: allow removing attributes from subsignals. tree | commitdiff
2019-07-08 whitequarkbuild.dsl: allow assertions on subsignal widths. tree | commitdiff
2019-07-08 whitequarkhdl.{ast,cd,dsl,xfrm}: reject inappropriately used... tree | commitdiff
2019-07-08 whitequarktest: generate examples to verilog as part of unit... tree | commitdiff
2019-07-08 whitequarkcompat.genlib.fsm: fix after commit dac62754. tree | commitdiff
2019-07-08 whitequarkhdl.xfrm: don't overwrite source locations on ClockDoma... tree | commitdiff
2019-07-08 whitequarkhdl.{dsl,mem,xfrm}: inject appropriate source locations. tree | commitdiff
2019-07-08 whitequarkback.rtlil: ignore empty source locations. tree | commitdiff
2019-07-08 whitequarkhdl.ast: use keyword-only arguments as appropriate. tree | commitdiff
2019-07-08 whitequarkback.rtlil: attach source locations to switches, not... tree | commitdiff
2019-07-08 whitequarkback.rtlil: use a more principled approach to attribute... tree | commitdiff
2019-07-07 Alain Péteutvendor.xilinx_7series: generate also binary bitfile. tree | commitdiff
2019-07-07 William D. Jonesvendor.xilinx_spartan_3_6: Add Spartan3A family support. tree | commitdiff
2019-07-07 whitequarkvendor.lattice_ecp5: don't leave LUT inputs disconnected. tree | commitdiff
2019-07-07 whitequarkhdl.dsl: further clarify error message for incorrect... tree | commitdiff
2019-07-07 whitequarkhdl.dsl: clarify error message for incorrect nesting. tree | commitdiff
2019-07-07 whitequarkhdl.dsl: gracefully handle FSM with no states. tree | commitdiff
2019-07-07 whitequarkbuild.plat: source a script with toolchain environment. tree | commitdiff
2019-07-07 whitequarkbuild.run: only use os.path on the target OS. tree | commitdiff
2019-07-07 whitequarkbuild.run: make BuildProducts abstract, add LocalBuildP... tree | commitdiff
2019-07-06 whitequarkbuild.plat, vendor.*: don't join strings passed as... tree | commitdiff
2019-07-06 whitequarkbuild.run: make sure BuildProducts._root is not easily... tree | commitdiff
2019-07-04 Staf Verhaegenvendor.xilinx_{7series,spartan6}: Support extra VHDL... tree | commitdiff
2019-07-03 whitequarkhdl.dsl: fix src_loc_at for FSM state signal. tree | commitdiff
2019-07-03 whitequarkback.rtlil: emit \src attributes for processes via... tree | commitdiff
2019-07-03 whitequarkhdl.ast: fix src_loc_at for Mux(). tree | commitdiff
2019-07-03 whitequarkbuild.res: detect physical conflicts earlier. tree | commitdiff
2019-07-03 whitequarkhdl.rec: thread src_loc_at to all inner Signals and... tree | commitdiff
2019-07-03 whitequarkvendor: give names to IO buffer instances. tree | commitdiff
2019-07-03 whitequarkhdl.rec: accept Record(src_loc_at=...). tree | commitdiff
2019-07-03 whitequarkcompat.fhdl.specials: mark CompatMemory as Elaboratable. tree | commitdiff
2019-07-03 whitequarkcompat.fhdl.specials: use "sync" as default domain... tree | commitdiff
2019-07-03 whitequarkcompat.fhdl.specials: fix Memory.get_port() after 94e8f479. tree | commitdiff
2019-07-03 whitequarkcompat.fhdl.structure: fix If/Elif/Else after 32446831. tree | commitdiff
2019-07-03 Sebastien Bourdeauducqlattice_ecp5: fix get_input tree | commitdiff
2019-07-02 whitequarkhdl.ast: recognize a Enum used as decoder and format... tree | commitdiff
2019-07-02 whitequarkhdl.mem: fix naming of registers inside unnamed memories. tree | commitdiff
2019-07-02 Alain Péteutbuild.plat: add iter_extra_files method. tree | commitdiff
2019-07-02 whitequarkback.rtlil: emit \sig$next wires instead of \$next... tree | commitdiff
2019-07-02 whitequarkback.rtlil: do not emit $next wires for comb signals. tree | commitdiff
2019-07-02 whitequarkhdl.rec: implement slicing by component names. tree | commitdiff
2019-07-02 whitequarkhdl.rec: implement Record.like. tree | commitdiff
2019-07-02 Alain Péteutvendor.xilinx_7series: read extra .xdc files. tree | commitdiff
2019-07-01 whitequarkhdl.mem: use read_port(domain="comb") for asynchronous... tree | commitdiff
2019-07-01 whitequarkback.rtlil: fix Array regression in 32446831. tree | commitdiff
2019-06-28 whitequarkback.pysim: create unique ResetSynchronizer internal... tree | commitdiff
2019-06-28 whitequarkback.pysim: override ResetSynchronizer implementation. tree | commitdiff
2019-06-28 whitequarklib.cdc: avoid interior clock domains in ResetSynchronizer. tree | commitdiff
2019-06-28 whitequarklib.cdc: eliminate no_retiming attributes. tree | commitdiff
2019-06-28 whitequarkvendor.lattice_ice40: fix instance of negedge FF due... tree | commitdiff
2019-06-28 Alain Péteutbuild.plat: fix dedent overrides. tree | commitdiff
2019-06-28 whitequarkhdl.{ast,dsl}, back.{pysim,rtlil}: allow multiple case... tree | commitdiff
2019-06-28 whitequarkhdl.ir, back.rtlil: allow specifying attributes on... tree | commitdiff
2019-06-26 whitequarkback.pysim: fix scope screwup. tree | commitdiff
2019-06-25 whitequarkcompat.fhdl.structure: fix typo. tree | commitdiff
2019-06-25 whitequarkcompat.fhdl.structure: simplify handling of default... tree | commitdiff
2019-06-25 whitequarkhdl.{ast,dst}: directly represent RTLIL default case. tree | commitdiff
2019-06-25 whitequarkvendor.xilinx_{spartan6,7series}: speedgrade→speed. tree | commitdiff
2019-06-25 whitequarkvendor.lattice_ecp5: implement. tree | commitdiff
2019-06-19 whitequarkvendor.lattice_ice40: use different --package for 4k... tree | commitdiff
2019-06-17 Jean-François Nguyenvendor.xilinx_7series: fix IOB packing. tree | commitdiff
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: emit IBUF/OBUF explic... tree | commitdiff
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: cleanup. NFC. tree | commitdiff
2019-06-17 whitequarkvendor.xilinx_{7series,spartan6}: connect FCDE and... tree | commitdiff
2019-06-16 Alain Péteutbuild.plat: dedent overrides. tree | commitdiff
2019-06-14 whitequarkvendor.lattice_ice40: never place an inverter on global... tree | commitdiff
2019-06-13 Jean-François Nguyenvendor.xilinx_7series: implement inverters. tree | commitdiff
2019-06-13 Jean-François Nguyenvendor.xilinx_spartan6: implement DDR I/O buffers and... tree | commitdiff
2019-06-13 whitequarkcompat.fhdl.structure: fix Case().makedefault(). tree | commitdiff
2019-06-13 whitequarkcompat.fhdl.structure: always order default case as... tree | commitdiff
2019-06-13 whitequarkhdl.ast: tighten assertion in Switch(). tree | commitdiff
2019-06-12 whitequarkSimplify code by using Signal.like(name_suffix="..... tree | commitdiff
2019-06-12 whitequarkhdl.ast: add name_suffix=".." option to Signal.like(). tree | commitdiff
2019-06-12 Jean-François Nguyenvendor.xilinx_7series: implement DDR I/O buffers. tree | commitdiff
2019-06-12 whitequarkvendor.lattice_ice40: fix typo. tree | commitdiff
2019-06-12 whitequarkbuild.{dsl,res,plat}: add PinsN and DiffPairsN. tree | commitdiff
2019-06-11 whitequarkhdl.ast: implement values with custom lowering. tree | commitdiff
2019-06-11 whitequarkback.pysim: check for a clock being added twice. tree | commitdiff
2019-06-11 whitequarkback.rtlil: mask memory init values. tree | commitdiff
2019-06-11 whitequarkhdl.mem: coerce memory init values to integers. tree | commitdiff
2019-06-09 Simon Kirkbylib.cdc: fix typo. tree | commitdiff
2019-06-07 Jean-François Nguyenvendor.xilinx_spartan6: implement. tree | commitdiff
2019-06-07 Jean-François Nguyenvendor.xilinx_7series: fix typos. tree | commitdiff
2019-06-06 whitequarkbuild.dsl: fix precondition check in Pins. tree | commitdiff
2019-06-06 Jean-François Nguyenvendor.xilinx_7series: implement. tree | commitdiff
2019-06-05 whitequarkbuild.res: allow querying frequency of a previously... tree | commitdiff
2019-06-05 whitequarkbuild.{dsl,res,plat}: apply clock constraints to signal... tree | commitdiff
2019-06-05 whitequarkbuild.dsl: replace extras= with Attrs(). tree | commitdiff
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