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back.pysim: close .vcd/.gtkw files on context manager exit.
[nmigen.git]
/
nmigen
/
2018-12-14
whitequark
back.pysim: close .vcd/.gtkw files on context manager...
tree
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commitdiff
2018-12-14
whitequark
back.pysim: show more legible names for processes in...
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commitdiff
2018-12-14
whitequark
back.pysim: throw exceptions back at processes.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: add gtkw traces even more robustly.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: accept (and evaluate) generator functions.
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commitdiff
2018-12-14
whitequark
back.pysim: skip VCD signal population if VCD is not...
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commitdiff
2018-12-14
whitequark
back.pysim: allow processes to evaluate expressions.
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commitdiff
2018-12-14
whitequark
fhdl.ir: oops, we defined DomainError twice.
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commitdiff
2018-12-14
whitequark
back.pysim: more general clean-up.
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commitdiff
2018-12-14
whitequark
back.pysim: general clean-up.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: accept any valid assignments from processes.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: robustly retrieve vcd names for clk/rst...
tree
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commitdiff
2018-12-14
whitequark
fhdl.xfrm: implement DomainLowerer.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: undriven comb signals should return to...
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commitdiff
2018-12-14
whitequark
ast, back.pysim: allow specifying user-defined decoders...
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commitdiff
2018-12-14
whitequark
back.pysim: fix completely broken codegen for Switch.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: raise an exception if delta cycles blow...
tree
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commitdiff
2018-12-14
whitequark
back.pysim: if requested, write a gtkw file with a...
tree
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commitdiff
2018-12-14
whitequark
back.pysim: explain how delta cycles work.
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commitdiff
2018-12-14
whitequark
back.pysim: delay clock processes by one half period.
tree
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commitdiff
2018-12-14
whitequark
back.pysim: implement "sync processes", like migen...
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commitdiff
2018-12-14
whitequark
back.pysim: allow suspending processes until a tick...
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commitdiff
2018-12-14
whitequark
back.pysim: use bare ints for signal values (-5% runtime).
tree
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commitdiff
2018-12-13
whitequark
back.pysim: collect handlers before running (-5% runtime).
tree
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commitdiff
2018-12-13
whitequark
back.pysim: allow multiple registered handlers per...
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commitdiff
2018-12-13
whitequark
back.pysim: fix handling of process termination.
tree
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commitdiff
2018-12-13
whitequark
back.pysim: new simulator backend (WIP).
tree
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commitdiff
2018-12-13
whitequark
fhdl.cd: rename ClockDomain signals together with domain.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: move Fragment prepare logic from back.rtlil.
tree
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commitdiff
2018-12-13
whitequark
back.verilog: remove debug code.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: record port direction explicitly.
tree
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commitdiff
2018-12-13
whitequark
compat.genlib.fsm: import/wrap Migen code.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: a subfragment's input that we don't drive...
tree
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commitdiff
2018-12-13
whitequark
fhdl, back: trace and emit source locations of values.
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: never give subfragment cells names starting...
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commitdiff
2018-12-13
whitequark
fhdl.ir: don't crash propagataing ports in empty fragments.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: implement clock domain propagation.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: remove iter_domains().
tree
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commitdiff
2018-12-13
whitequark
fhdl: cd_name→domain.
tree
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commitdiff
2018-12-13
whitequark
fhdl.cd: add tests.
tree
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commitdiff
2018-12-13
whitequark
fhdl.xfrm: implement DomainRenamer.
tree
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commitdiff
2018-12-13
whitequark
fhdl.xfrm: add test for ControlInserter with subfragments.
tree
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commitdiff
2018-12-13
whitequark
fhdl.xfrm: add tests for ResetInserter, CEInserter.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: add tests for port propagation.
tree
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commitdiff
2018-12-13
whitequark
fhdl.dsl: add tests for lowering. 99% branch coverage.
tree
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commitdiff
2018-12-13
whitequark
fhdl.cd: rename ClockDomain.{reset→rst}.
tree
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commitdiff
2018-12-13
whitequark
fhdl.dsl: add tests for submodules.
tree
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commitdiff
2018-12-13
whitequark
fhdl.dsl: use less error-prone Switch/Case two-level...
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commitdiff
2018-12-13
whitequark
fhdl.dsl: add tests for d.comb/d.sync, If/Elif/Else.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ast: fix Switch._?hs_signals() for switch without...
tree
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commitdiff
2018-12-13
whitequark
back.verilog: detect undriven public wires using Yosys.
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: fix swapped operands in sync assign.
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: explain logic for CD reset insertion.
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: explicitly set the top module.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: explain how port enumeration works.
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: explain how RTLIL conversion works.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ir: make sure clocks and resets of used CDs appear...
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: give clocks and resets nicer names.
tree
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commitdiff
2018-12-13
whitequark
compat.fhdl.module: implement finalization.
tree
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commitdiff
2018-12-13
whitequark
back.rtlil: match shape of $mux ports A/B/Y.
tree
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commitdiff
2018-12-13
whitequark
tracer: add support for Python 3.7.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ast: bits_sign→shape.
tree
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commitdiff
2018-12-13
whitequark
fhdl.ast: add tests for most logic.
tree
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commitdiff
2018-12-12
whitequark
compat.fhdl.{module,structure}: import/wrap Migen code...
tree
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commitdiff
2018-12-12
whitequark
compat.fhdl.bitcontainer: import/wrap Migen code.
tree
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commitdiff
2018-12-12
whitequark
fhdl.ast.Signal: implement .like().
tree
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commitdiff
2018-12-12
whitequark
fhdl.ir: fix port threading code.
tree
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commitdiff
2018-12-12
whitequark
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
tree
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commitdiff
2018-12-12
whitequark
fhdl.ast.Signal: fix typo.
tree
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commitdiff
2018-12-12
whitequark
fhdl.ast.Signal: implement attrs field.
tree
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commitdiff
2018-12-12
whitequark
genlib.cdc.MultiReg: self.regs should be a private...
tree
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commitdiff
2018-12-12
whitequark
fhdl.ast.Signal: implement width derivation from min...
tree
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commitdiff
2018-12-12
whitequark
genlib.cdc.MultiReg: pull in from Migen.
tree
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commitdiff
2018-12-12
whitequark
fhdl.ast.Signal: implement reset_less signals.
tree
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commitdiff
2018-12-12
whitequark
fhdl.ast.Signal: assign an internal name if tracer...
tree
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commitdiff
2018-12-12
whitequark
fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync...
tree
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commitdiff
2018-12-12
whitequark
ClockDomain.{rst→reset}, for consistency with ResetInse...
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commitdiff
2018-12-12
whitequark
Initial commit.
tree
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commitdiff