| 2016-11-11 |
Szabolcs Nagy | [AArch64] Add ARMv8.3 pointer authentication key registers |
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| 2016-11-11 |
Szabolcs Nagy | [AArch64] Add ARMv8.3 instructions which are in the... |
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| 2016-11-11 |
Szabolcs Nagy | [AArch64] Increase max_num_aliases in aarch64-gen |
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| 2016-11-09 |
H.J. Lu | X86: Remove the .s suffix from EVEX vpextrw |
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| 2016-11-09 |
H.J. Lu | Update opcodes/ChangeLog |
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| 2016-11-09 |
H.J. Lu | X86: Merge AVX512F vmovq |
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| 2016-11-08 |
H.J. Lu | X86: Remove the THREE_BYTE_0F7A entry |
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| 2016-11-07 |
H.J. Lu | X86: Properly handle bad FPU opcode |
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| 2016-11-04 |
Andrew Burgess | arc/nps400: Validate address type operands correctly |
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| 2016-11-03 |
Graham Markall | arc: Implement NPS-400 dcmac instruction |
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| 2016-11-03 |
Andrew Burgess | arc: Change max instruction length to 64-bits |
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| 2016-11-03 |
Graham Markall | arc: Swap highbyte and lowbyte in print_insn_arc |
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| 2016-11-03 |
Graham Markall | arc: Replace ARC_SHORT macro with arc_opcode_len function |
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| 2016-11-03 |
Andrew Burgess | arc/opcodes/nps400: Fix some instruction masks |
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| 2016-11-03 |
H.J. Lu | X86: Reuse opcode 0x80 decoder for opcode 0x82 |
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| 2016-11-03 |
H.J. Lu | X86: Decode opcode 0x82 as opcode 0x80 in 32-bit mode |
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| 2016-11-03 |
H.J. Lu | X86: Rename REG_82 to REG_83 |
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| 2016-11-02 |
Igor Tsimbalist | Enable Intel AVX512_4VNNIW instructions |
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| 2016-11-02 |
Igor Tsimbalist | Enable Intel AVX512_4FMAPS instructions |
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| 2016-11-01 |
Nick Clifton | Add support for RISC-V architecture. |
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| 2016-10-21 |
H.J. Lu | X86: Remove pcommit instruction |
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| 2016-10-20 |
H.J. Lu | Check invalid mask registers |
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| 2016-10-18 |
H.J. Lu | Check addr32flag instead of sizeflag for rip/eip |
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| 2016-10-18 |
H.J. Lu | Remove the remaining SSE5 support |
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| 2016-10-18 |
Maciej W. Rozycki | AArch64/opcodes: Correct an `index' global shadowing... |
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| 2016-10-17 |
Cupertino Miranda | Removed pseudo invalid instructions opcodes. |
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| 2016-10-14 |
Claudiu Zissulescu | [ARC] Disassembler: fix LIMM detection for short instru... |
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| 2016-10-11 |
Jiong Wang | [AArch64] PR target/20666, fix wrong encoding of new... |
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| 2016-10-07 |
Jiong Wang | [AArch64] PR target/20667, fix disassembler for the... |
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| 2016-10-07 |
Alan Modra | bfd_merge_private_bfd_data tidy |
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| 2016-10-05 |
Alan Modra | -Wimplicit-fallthrough warning fixes |
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| 2016-10-05 |
Alan Modra | -Wimplicit-fallthrough error fixes |
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| 2016-10-05 |
Alan Modra | Don't use boolean OR in arithmetic expressions |
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| 2016-09-30 |
H.J. Lu | Don't assign alt twice |
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| 2016-09-30 |
Jiong Wang | [AArch64] PR target/20553, fix opcode mask for SIMD... |
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| 2016-09-29 |
Alan Modra | Disallow 3-operand cmp[l][i] for ppc64 |
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| 2016-09-26 |
Vlad Zakharov | When building target binaries, ensure that the warning... |
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| 2016-09-26 |
Claudiu Zissulescu | [ARC] ISA alignment. |
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| 2016-09-21 |
Richard Sandiford | [AArch64] Print spaces after commas in addresses |
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| 2016-09-21 |
Richard Sandiford | [AArch64] Use "must" rather than "should" in error... |
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| 2016-09-21 |
Richard Sandiford | [AArch64] Add SVE condition codes |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 31/32] Add SVE instructions |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 30/32] Add SVE instruction classes |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 29/32] Add new SVE core & FP register... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 28/32] Add SVE FP immediate operands |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 27/32] Add SVE integer immediate operands |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 26/32] Add SVE MUL VL addressing modes |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 25/32] Add support for SVE addressing... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 24/32] Add AARCH64_OPND_SVE_PATTERN_SCALED |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 23/32] Add SVE pattern and prfop operands |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 22/32] Add qualifiers for merging and... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 21/32] Add Zn and Pn registers |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 20/32] Add support for tied operands |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 19/32] Refactor address-printing code |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 18/32] Tidy definition of aarch64-opc... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 17/32] Add a prefix parameter to print_re... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 16/32] Use specific insert/extract method... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 15/32] Add {insert,extract}_all_fields... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 14/32] Make aarch64_logical_immediate_p... |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 13/32] Add an F_STRICT flag |
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| 2016-09-21 |
Richard Sandiford | [AArch64][SVE 02/32] Avoid hard-coded limit in indented... |
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| 2016-09-16 |
Claudiu Zissulescu | [ARC] Disassemble correctly extension instructions. |
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| 2016-09-15 |
Peter Bergner | Modify POWER9 support to match final ISA 3.0 documentation. |
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| 2016-09-14 |
Anton Kolesov | Stop the ARC disassembler from seg-faulting if initiali... |
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| 2016-09-12 |
Andreas Krebbel | S/390: Add alternate processor names. |
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| 2016-09-12 |
Patrick Steuer | S/390: Fix kmctr instruction type. |
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| 2016-09-07 |
H.J. Lu | X86: Allow additional ISAs for IAMCU in assembler |
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| 2016-08-30 |
Cupertino Miranda | Fixed issue with NULL pointer access on header var. |
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| 2016-08-26 |
Jose E. Marchesi | opcodes, gas: fix mnemonic of sparc camellia_fl |
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| 2016-08-26 |
Thomas Preud'homme | Add missing ARMv8-M special registers |
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| 2016-08-24 |
H.J. Lu | X86: Add ptwrite instruction |
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| 2016-08-24 |
Anton Kolesov | [ARC] C++ compatibility for arc-dis.h |
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| 2016-08-23 |
Richard Sandiford | [AArch64] Add V8_2_INSN macro |
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| 2016-08-23 |
Richard Sandiford | [AArch64] Make more use of CORE/FP/SIMD_INSN |
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| 2016-08-23 |
Richard Sandiford | [AArch64] Add OP parameter to aarch64-tbl.h macros |
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| 2016-08-01 |
Andrew Jenner | Fix some PowerPC VLE BFD issues and add some... |
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| 2016-07-27 |
Maciej W. Rozycki | MIPS/GAS: Implement microMIPS branch/jump compaction |
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| 2016-07-27 |
Graham Markall | Begin implementing ARC NPS-400 Accelerator instructions |
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| 2016-07-21 |
H.J. Lu | Set BFD_VERSION to 2.27.51 |
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| 2016-07-20 |
Claudiu Zissulescu | Add support to the ARC disassembler for selecting instr... |
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| 2016-07-13 |
Maciej W. Rozycki | MIPS/opcodes: Address issues with NAL disassembly |
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| 2016-07-13 |
Jose E. Marchesi | opcodes,gas: support for the ldtxa SPARC instructions. |
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| 2016-07-08 |
jamesbowman | FT32: adjust disassembly opcode match fields |
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| 2016-07-01 |
Jan Beulich | x86: allow suffix-less movzw and 64-bit movzb |
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| 2016-07-01 |
Jan Beulich | x86: remove stray instruction attributes |
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| 2016-07-01 |
Jan Beulich | x86/Intel: fix operand checking for MOVSD |
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| 2016-06-30 |
Yao Qi | Fix typo in comment |
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| 2016-06-28 |
Richard Sandiford | [AArch64] Make register indices be full 64-bit values |
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| 2016-06-25 |
Trevor Saunders | remove a few sentinals |
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| 2016-06-23 |
Graham Markall | [ARC] Misc minor edits/fixes |
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| 2016-06-22 |
Peter Bergner | Add support for yet some more new ISA 3.0 instructions. |
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| 2016-06-22 |
Trevor Saunders | addmore extern C |
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| 2016-06-21 |
Graham Markall | Arc assembler: Convert nps400 from a machine type to... |
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| 2016-06-17 |
Jose E. Marchesi | opcodes,gas: sparc: fix rdasr,wrasr,rdpr,wrpr,rdhpr... |
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| 2016-06-17 |
Jose E. Marchesi | opcodes,gas: adjust sparc insns and make GAS aware... |
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| 2016-06-17 |
Jose E. Marchesi | bfd,opcodes: sparc: new opcode v9{c,d,e,v,m} architectu... |
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| 2016-06-15 |
Nick Clifton | Fix simple gas testsuite failures. |
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| 2016-06-15 |
Andrew Burgess | opcodes/arc: Fix extract for some add_s instructions |
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| 2016-06-14 |
Graham Markall | opcode/gas: Fix incorrect dates on ChangeLog entries |
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| 2016-06-14 |
Graham Markall | [ARC] Add ldbit for nps |
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