| 2022-12-19 |
Jan Beulich | x86: omit Cpu prefixes from opcode table |
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| 2022-12-16 |
Jan Beulich | x86: change representation of extension opcode |
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| 2022-12-12 |
Jan Beulich | x86: further re-work insn/suffix recognition to also... |
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| 2022-12-12 |
Jan Beulich | x86: drop (now) stray IsString |
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| 2022-12-12 |
Jan Beulich | x86: re-work insn/suffix recognition |
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| 2022-12-03 |
H.J. Lu | x86: Allow 16-bit register source for LAR and LSL |
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| 2022-12-02 |
Jan Beulich | x86: also use D for XCHG and TEST |
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| 2022-12-01 |
Jan Beulich | x86: drop No_ldSuf |
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| 2022-12-01 |
Jan Beulich | x86/Intel: drop LONG_DOUBLE_MNEM_SUFFIX |
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| 2022-12-01 |
Jan Beulich | x86/Intel: restrict use of LONG_DOUBLE_MNEM_SUFFIX |
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| 2022-11-30 |
Jan Beulich | x86: clean up after removal of support for gcc <= 2.8.1 |
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| 2022-11-30 |
Jan Beulich | x86: drop FloatR |
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| 2022-11-24 |
Jan Beulich | x86: widen applicability and use of CheckRegSize |
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| 2022-11-24 |
Jan Beulich | x86: add missing CheckRegSize |
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| 2022-11-24 |
Jan Beulich | x86: correct handling of LAR and LSL |
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| 2022-11-17 |
H.J. Lu | opcodes: Define NoSuf in i386-opc.tbl |
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| 2022-11-15 |
Tejas Joshi | Add AMD znver4 processor support |
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| 2022-11-14 |
Jan Beulich | x86: fold special-operand insn attributes into a single... |
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| 2022-11-11 |
Jan Beulich | x86: drop stray IsString from PadLock insns |
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| 2022-11-08 |
Kong Lingling | Support Intel RAO-INT |
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| 2022-11-04 |
konglin1 | Support Intel AVX-NE-CONVERT |
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| 2022-11-04 |
konglin1 | i386: Rename <xy> template. |
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| 2022-11-02 |
Jan Beulich | x86: drop bogus Tbyte |
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| 2022-11-02 |
Hu, Lin1 | Support Intel MSRLIST |
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| 2022-11-02 |
Hu, Lin1 | Support Intel WRMSRNS |
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| 2022-11-02 |
Haochen Jiang | Support Intel CMPccXADD |
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| 2022-11-02 |
Cui,Lili | Support Intel AVX-VNNI-INT8 |
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| 2022-11-02 |
Hongyu Wang | Support Intel AVX-IFMA |
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| 2022-10-31 |
Cui, Lili | Support Intel PREFETCHI |
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| 2022-10-21 |
Cui,Lili | Support Intel AMX-FP16 |
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| 2022-10-20 |
Jan Beulich | x86: re-work AVX-VNNI support |
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| 2022-09-30 |
Jan Beulich | x86/Intel: restrict suffix derivation |
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| 2022-08-16 |
Jan Beulich | x86: shorten certain template names |
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| 2022-08-16 |
Jan Beulich | x86: template-ize certain vector conversion insns |
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| 2022-08-16 |
Jan Beulich | x86: template-ize vector packed byte/word integer insns |
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| 2022-08-16 |
Jan Beulich | x86: re-order AVX512 S/G templates |
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| 2022-08-16 |
Jan Beulich | x86: template-ize vector packed dword/qword integer... |
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| 2022-08-16 |
Jan Beulich | x86: template-ize packed/scalar vector floating point... |
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| 2022-08-16 |
Jan Beulich | revert "x86: Also pass -P to $(CPP) when processing... |
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| 2022-08-09 |
Jan Beulich | x86-64: adjust MOVQ to/from SReg attributes |
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| 2022-08-09 |
Jan Beulich | x86: adjust MOVSD attributes |
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| 2022-08-09 |
Jan Beulich | x86: fold AVX VGATHERDPD / VPGATHERDQ |
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| 2022-08-09 |
Jan Beulich | x86: allow use of broadcast with X/Y/Z-suffixed AVX512... |
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| 2022-08-09 |
Jan Beulich | x86/Intel: split certain AVX512-FP16 VCVT*2PH templates |
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| 2022-08-03 |
Jan Beulich | x86: properly mark i386-only insns |
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| 2022-08-03 |
Jan Beulich | x86: also use D for MOVBE |
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| 2022-08-02 |
Jan Beulich | x86: XOP shift insns don't really allow B suffix |
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| 2022-08-01 |
Jan Beulich | x86: SKINIT with operand needs IgnoreSize |
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| 2022-07-29 |
Jan Beulich | x86: drop stray NoRex64 from KeyLocker insns |
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| 2022-07-21 |
Jan Beulich | x86: replace wrong attributes on VCVTDQ2PH{X,Y} |
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| 2022-07-21 |
Jan Beulich | x86/Intel: correct AVX512F scatter insn element sizes |
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| 2022-07-18 |
Jan Beulich | x86: correct VMOVSH attributes |
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| 2022-07-06 |
Jan Beulich | x86: make D attribute usable for XOP and FMA4 insns |
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| 2022-07-04 |
Jan Beulich | x86: fold Disp32S and Disp32 |
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| 2022-06-29 |
Jan Beulich | x86: drop stray NoRex64 from XBEGIN |
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| 2022-05-27 |
Jan Beulich | x86: re-work AVX512 embedded rounding / SAE |
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| 2022-04-27 |
Jan Beulich | x86: VFPCLASSSH is Evex.LLIG |
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| 2022-04-19 |
Jan Beulich | x86: VCMPSH is Evex.LLIG |
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| 2022-04-19 |
Jan Beulich | x86: drop stray CheckRegSize from VFPCLASSPH |
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| 2022-03-18 |
Jan Beulich | x86: also fold remaining multi-vector-size shift insns |
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| 2022-03-18 |
Jan Beulich | x86: drop stray CheckRegSize from VEXTRACT{F,I}32X4 |
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| 2022-03-18 |
Jan Beulich | x86: fold certain AVX2 templates into their AVX counter... |
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| 2022-01-06 |
Jan Beulich | x86: drop NoAVX insn attribute |
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| 2022-01-06 |
Jan Beulich | x86: drop NoAVX from POPCNT |
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| 2022-01-06 |
Jan Beulich | x86: drop some "comm" template parameters |
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| 2022-01-06 |
Jan Beulich | x86: templatize FMA insn templates |
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| 2022-01-02 |
Alan Modra | Update year range in copyright notice of binutils files |
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| 2021-08-05 |
Cui,Lili | [PATCH 1/2] Enable Intel AVX512_FP16 instructions |
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| 2021-07-14 |
H.J. Lu | x86: Add int1 as one byte opcode 0xf1 |
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| 2021-04-26 |
Jan Beulich | x86: optimize LEA |
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| 2021-03-29 |
Jan Beulich | x86: move some opcode table entries |
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| 2021-03-29 |
Jan Beulich | x86: VPSADBW's source operands are also commutative |
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| 2021-03-29 |
Jan Beulich | x86: fold SSE2AVX and their base MMX/SSE templates |
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| 2021-03-29 |
Jan Beulich | x86: undo Prefix_0X<nn> use in opcode table |
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| 2021-03-26 |
Jan Beulich | x86-64: don't accept supposedly disabled MOVQ forms |
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| 2021-03-25 |
Jan Beulich | x86: fix AMD Zen3 insns |
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| 2021-03-24 |
Jan Beulich | x86: derive opcode length from opcode value |
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| 2021-03-24 |
Jan Beulich | x86: don't use opcode_length to identify pseudo prefixes |
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| 2021-03-23 |
Jan Beulich | x86: split opcode prefix and opcode space representation |
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| 2021-03-09 |
Jan Beulich | x86: fold some prefix related attributes into a single one |
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| 2021-03-09 |
Jan Beulich | x86-64: make SYSEXIT handling similar to SYSRET's |
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| 2021-03-03 |
Jan Beulich | x86: infer operand count of templates |
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| 2021-02-16 |
Jan Beulich | x86: CVTPI2PD has special behavior |
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| 2021-02-16 |
Jan Beulich | x86: have preprocessor expand macros |
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| 2021-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
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| 2020-10-20 |
Ganesh Gopalasubra... | Add AMD znver3 processor support |
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| 2020-10-16 |
Cui,Lili | Enhancement for avx-vnni patch |
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| 2020-10-14 |
H.J. Lu | x86: Support Intel AVX VNNI |
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| 2020-10-14 |
Lili Cui | x86: Add support for Intel HRESET instruction |
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| 2020-10-14 |
Lili Cui | x86: Support Intel UINTR |
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| 2020-10-14 |
H.J. Lu | x86: Remove the prefix byte from non-VEX/EVEX base_opcode |
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| 2020-10-14 |
H.J. Lu | x86: Rename VexOpcode to OpcodePrefix |
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| 2020-09-24 |
Cui,Lili | Add support for Intel TDX instructions. |
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| 2020-09-23 |
Terry Guo | Enable support to Intel Keylocker instructions |
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| 2020-07-30 |
H.J. Lu | x86: Add {disp16} pseudo prefix |
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| 2020-07-10 |
Lili Cui | x86: Add support for Intel AMX instructions |
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| 2020-07-08 |
Jan Beulich | x86: FMA4 scalar insns ignore VEX.L |
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| 2020-07-02 |
H.J. Lu | x86: Add SwapSources |
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| 2020-06-26 |
H.J. Lu | i386-opc.tbl: Add a blank line |
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| 2020-06-26 |
H.J. Lu | x86: Correct VexSIB128 to VecSIB128 |
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