| 2022-05-20 |
Jia-Wei Chen | RISC-V: Update zfinx implement with zicsr. |
blob | commitdiff | raw |
| 2022-05-20 |
Tsukasa OI | RISC-V: Remove RV128-only fmv instructions |
blob | commitdiff | raw | diff to current |
| 2022-05-17 |
Nelson Chu | RISC-V: Added half-precision floating-point v1.0 instru... |
blob | commitdiff | raw | diff to current |
| 2022-03-29 |
Jan Beulich | RISC-V: correct FCVT.Q.L[U] |
blob | commitdiff | raw | diff to current |
| 2022-03-18 |
Tsukasa OI | RISC-V: Cache management instructions |
blob | commitdiff | raw | diff to current |
| 2022-03-18 |
Tsukasa OI | RISC-V: Prefetch hint instructions and operand set |
blob | commitdiff | raw | diff to current |
| 2022-02-25 |
Tsukasa OI | RISC-V: Fix mask for some fcvt instructions |
blob | commitdiff | raw | diff to current |
| 2022-01-02 |
Alan Modra | Update year range in copyright notice of binutils files |
blob | commitdiff | raw | diff to current |
| 2021-12-24 |
Vineet Gupta | RISC-V: Hypervisor ext: support Privileged Spec 1.12 |
blob | commitdiff | raw | diff to current |
| 2021-12-16 |
Nelson Chu | RISC-V: Support svinval extension with frozen version... |
blob | commitdiff | raw | diff to current |
| 2021-11-30 |
Nelson Chu | RISC-V: Dump vset[i]vli immediate as numbers once vsew... |
blob | commitdiff | raw | diff to current |
| 2021-11-18 |
jiawei | RISC-V: Add instructions and operand set for z[fdq]inx |
blob | commitdiff | raw | diff to current |
| 2021-11-17 |
Nelson Chu | RISC-V: Support rvv extension with released version... |
blob | commitdiff | raw | diff to current |
| 2021-11-16 |
jiawei | RISC-V: Scalar crypto instructions and operand set. |
blob | commitdiff | raw | diff to current |
| 2021-10-07 |
Philipp Tomsich | RISC-V: Support aliases for Zbs instructions |
blob | commitdiff | raw | diff to current |
| 2021-10-07 |
Philipp Tomsich | RISC-V: Add support for Zbs instructions |
blob | commitdiff | raw | diff to current |
| 2021-10-07 |
Philipp Tomsich | RISC-V: Split Zb[abc] into commented sections |
blob | commitdiff | raw | diff to current |
| 2021-04-16 |
Lifang Xia | RISC-V: compress "addi d,CV,z" to "c.mv d,CV" |
blob | commitdiff | raw | diff to current |
| 2021-03-16 |
Kuan-Lin Chen | RISC-V : Support bitmanip-0.93 ZBA/ZBB/ZBC instructions |
blob | commitdiff | raw | diff to current |
| 2021-02-19 |
Nelson Chu | RISC-V: PR27158, fixed UJ/SB types and added CSS/CL... |
blob | commitdiff | raw | diff to current |
| 2021-02-18 |
Nelson Chu | RISC-V: Add bfd/cpu-riscv.h to support all spec version... |
blob | commitdiff | raw | diff to current |
| 2021-02-04 |
Nelson Chu | RISC-V: Removed the v0.93 bitmanip ZBA/ZBB/ZBC instruct... |
blob | commitdiff | raw | diff to current |
| 2021-01-15 |
Nelson Chu | RISC-V: Indent and GNU coding standards tidy, also... |
blob | commitdiff | raw | diff to current |
| 2021-01-15 |
Nelson Chu | RISC-V: Comments tidy and improvement. |
blob | commitdiff | raw | diff to current |
| 2021-01-07 |
Philipp Tomsich | RISC-V: Add pause hint instruction. |
blob | commitdiff | raw | diff to current |
| 2021-01-07 |
Claire Xenia Wolf | RISC-V: Support riscv bitmanip frozen ZBA/ZBB/ZBC instr... |
blob | commitdiff | raw | diff to current |
| 2021-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
blob | commitdiff | raw | diff to current |
| 2020-12-10 |
Nelson Chu | RISC-V: Add sext.[bh] and zext.[bhw] pseudo instructions. |
blob | commitdiff | raw | diff to current |
| 2020-12-10 |
Nelson Chu | RISC-V: Control fence.i and csr instructions by zifence... |
blob | commitdiff | raw | diff to current |
| 2020-12-01 |
Nelson Chu | RISC-V: Remove the unimplemented extensions. |
blob | commitdiff | raw | diff to current |
| 2020-12-01 |
Nelson Chu | RISC-V: Add zifencei and prefixed h class extensions. |
blob | commitdiff | raw | diff to current |
| 2020-06-22 |
Nelson Chu | RISC-V: Report warning when linking the objects with... |
blob | commitdiff | raw | diff to current |
| 2020-06-12 |
Nelson Chu | RISC-V: Drop the privileged spec v1.9 support. |
blob | commitdiff | raw | diff to current |
| 2020-06-03 |
Nelson Chu | RISC-V: Fix the error when building RISC-V linux native... |
blob | commitdiff | raw | diff to current |
| 2020-05-20 |
Nelson Chu | [PATCH v2 0/9] RISC-V: Support version controling for... |
blob | commitdiff | raw | diff to current |
| 2020-02-19 |
Jim Wilson | RISC-V: Convert the ADD/ADDI to the compressed MV/LI... |
blob | commitdiff | raw | diff to current |
| 2020-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
blob | commitdiff | raw | diff to current |
| 2019-11-13 |
Jim Wilson | RISC-V: Support the INSN_CLASS.*F.* classes for .insn... |
blob | commitdiff | raw | diff to current |
| 2019-09-18 |
Jim Wilson | RISC-V: Gate opcode tables by enum rather than string. |
blob | commitdiff | raw | diff to current |
| 2019-07-30 |
Jim Wilson | RISC-V: Fix minor issues with FP csr instructions. |
blob | commitdiff | raw | diff to current |
| 2019-07-05 |
Jim Wilson | Kito's 5-part patch set to improve .insn support. |
blob | commitdiff | raw | diff to current |
| 2019-02-08 |
Jim Wilson | RISC-V: Compress 3-operand beq/bne against x0. |
blob | commitdiff | raw | diff to current |
| 2019-01-01 |
Alan Modra | Update year range in copyright notice of binutils files |
blob | commitdiff | raw | diff to current |
| 2018-12-07 |
Jim Wilson | RISC-V: Fix 4-arg add parsing. |
blob | commitdiff | raw | diff to current |
| 2018-11-29 |
Jim Wilson | RISC-V: Add missing c.unimp instruction. |
blob | commitdiff | raw | diff to current |
| 2018-11-27 |
Jim Wilson | RISC-V: Add .insn CA support. |
blob | commitdiff | raw | diff to current |
| 2018-10-02 |
Palmer Dabbelt | RISC-V: Add fence.tso instruction |
blob | commitdiff | raw | diff to current |
| 2018-09-17 |
Jim Wilson | RISC-V: bge[u] should get higher priority than ble[u]. |
blob | commitdiff | raw | diff to current |
| 2018-08-31 |
Jim Wilson | RISC-V: Correct the requirement of compressed floating... |
blob | commitdiff | raw | diff to current |
| 2018-08-30 |
Jim Wilson | RISC-V: Allow instruction require more than one extension |
blob | commitdiff | raw | diff to current |
| 2018-07-30 |
Jim Wilson | RISC-V: Set insn info fields correctly when disassembling. |
blob | commitdiff | raw | diff to current |
| 2018-06-20 |
Sebastian Huber | RISC-V: Accept constant operands in la and lla |
blob | commitdiff | raw | diff to current |
| 2018-05-08 |
Jim Wilson | RISC-V: Add missing hint instructions from RV128I. |
blob | commitdiff | raw | diff to current |
| 2018-03-14 |
Jim Wilson | RISC-V: Add .insn support. |
blob | commitdiff | raw | diff to current |
| 2018-01-17 |
Jim Wilson | RISC-V: Fix bug in prior addi/c.nop patch. |
blob | commitdiff | raw | diff to current |
| 2018-01-15 |
Jim Wilson | RISC-V: Add support for addi that compresses to c.nop. |
blob | commitdiff | raw | diff to current |
| 2018-01-03 |
Alan Modra | Update year range in copyright notice of binutils files |
blob | commitdiff | raw | diff to current |
| 2017-12-20 |
Jim Wilson | RISC-V: Add compressed instruction hints, and a few... |
blob | commitdiff | raw | diff to current |
| 2017-12-13 |
Jim Wilson | Add missing RISC-V fsrmi and fsflagsi instructions. |
blob | commitdiff | raw | diff to current |
| 2017-10-24 |
Andrew Waterman | RISC-V: Fix disassembly of c.addi4spn, c.addi16sp,... |
blob | commitdiff | raw | diff to current |
| 2017-09-27 |
Nick Clifton | Add support for the new names of the RISC-V fmv.x.s... |
blob | commitdiff | raw | diff to current |
| 2017-08-22 |
Palmer Dabbelt | RISC-V: Mark "c.nop" as an alias |
blob | commitdiff | raw | diff to current |
| 2017-06-23 |
Andrew Waterman | RISC-V: Fix SLTI disassembly |
blob | commitdiff | raw | diff to current |
| 2017-05-02 |
Michael Clark | RISC-V: Change CALL macro to use ra as the temporary... |
blob | commitdiff | raw | diff to current |
| 2017-03-15 |
Kito Cheng | RISC-V: Fix assembler for c.li, c.andi and c.addiw |
blob | commitdiff | raw | diff to current |
| 2017-03-15 |
Kito Cheng | RISC-V: Fix assembler for c.addi, rd can be x0 |
blob | commitdiff | raw | diff to current |
| 2017-03-14 |
Andrew Waterman | RISC-V: Fix [dis]assembly of srai/srli |
blob | commitdiff | raw | diff to current |
| 2017-02-15 |
Andrew Waterman | Add SFENCE.VMA instruction |
blob | commitdiff | raw | diff to current |
| 2017-01-03 |
Kito Cheng | Add support for the Q extension to the RISCV ISA. |
blob | commitdiff | raw | diff to current |
| 2017-01-02 |
Alan Modra | Update year range in copyright notice of all files. |
blob | commitdiff | raw | diff to current |
| 2016-12-21 |
Andrew Waterman | Avoid creating symbol table entries for registers |
blob | commitdiff | raw | diff to current |
| 2016-12-20 |
Andrew Waterman | Correct assembler mnemonic for RISC-V aqrl AMOs |
blob | commitdiff | raw | diff to current |
| 2016-12-20 |
Andrew Waterman | Fix disassembly of RISC-V CSR instructions under -Mno... |
blob | commitdiff | raw | diff to current |
| 2016-12-20 |
Andrew Waterman | Add canonical JALR for RISC-V |
blob | commitdiff | raw | diff to current |
| 2016-12-20 |
Andrew Waterman | Formatting changes for RISC-V |
blob | commitdiff | raw | diff to current |
| 2016-11-01 |
Nick Clifton | Add support for RISC-V architecture. |
blob | commitdiff | raw | diff to current |
|
projects / binutils-gdb.git / history