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Add M32R_ARG_REGISTER_SIZE
[binutils-gdb.git]
/
opcodes
/
riscv-opc.c
2017-03-15
Kito Cheng
RISC-V: Fix assembler for c.li, c.andi and c.addiw
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2017-03-15
Kito Cheng
RISC-V: Fix assembler for c.addi, rd can be x0
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2017-03-14
Andrew Waterman
RISC-V: Fix [dis]assembly of srai/srli
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2017-02-15
Andrew Waterman
Add SFENCE.VMA instruction
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2017-01-03
Kito Cheng
Add support for the Q extension to the RISCV ISA.
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2017-01-02
Alan Modra
Update year range in copyright notice of all files.
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2016-12-21
Andrew Waterman
Avoid creating symbol table entries for registers
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2016-12-20
Andrew Waterman
Correct assembler mnemonic for RISC-V aqrl AMOs
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2016-12-20
Andrew Waterman
Fix disassembly of RISC-V CSR instructions under -Mno...
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2016-12-20
Andrew Waterman
Add canonical JALR for RISC-V
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2016-12-20
Andrew Waterman
Formatting changes for RISC-V
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2016-11-01
Nick Clifton
Add support for RISC-V architecture.
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