Automatic date update in version.in
[binutils-gdb.git] / opcodes /
2022-04-01 H.J. Lux86: Remove bfd_arch_l1om and bfd_arch_k1om
2022-03-31 Richard Sandifordaarch64: Relax check for RNG system registers
2022-03-29 Jan BeulichRISC-V: correct FCVT.Q.L[U]
2022-03-25 Nick Alcocklibtool.m4: fix the NM="/nm/over/here -B/option/with...
2022-03-24 Jan Beulichx86: drop L1OM special case from disassembler
2022-03-20 liuzhensonggas:LoongArch: Fix segment error in compilation due...
2022-03-20 liuzhensongubsan: loongarch : signed integer shift overflow.
2022-03-18 Jan Beulichx86: also fold remaining multi-vector-size shift insns
2022-03-18 Jan Beulichx86: drop stray CheckRegSize from VEXTRACT{F,I}32X4
2022-03-18 Jan Beulichx86: fold certain AVX2 templates into their AVX counter...
2022-03-18 Tsukasa OIRISC-V: Cache management instructions
2022-03-18 Tsukasa OIRISC-V: Prefetch hint instructions and operand set
2022-03-17 Jan Beulichx86: never set i386_cpu_flags' "unused" field
2022-03-17 Jan Beulichx86: unify CPU flag on/off processing
2022-03-17 Jan Beulichx86: drop L1OM/K1OM support from gas
2022-03-17 Jan Beulichx86: assorted IAMCU CPU checking fixes
2022-03-16 Simon Marchiopcodes: handle bfd_amdgcn_arch in configure script
2022-03-15 Alan ModraDelete PowerPC macro insn support
2022-03-15 Alan ModraPowerPC SPE/SPE2 aliases in powerpc_macros
2022-03-15 Alan ModraPowerPC VLE extended instructions in powerpc_macros
2022-03-15 Alan ModraPowerPC32 extended instructions in powerpc_macros
2022-03-15 Alan ModraPowerPC64 extended instructions in powerpc_macros
2022-03-13 Alan ModraPR28959, obdump doesn't disassemble mftb instruction
2022-03-06 Maciej W. RozyckiMIPS/opcodes: Fix alias annotation for branch instructions
2022-02-25 Tsukasa OIRISC-V: Fix mask for some fcvt instructions
2022-02-17 Nick CliftonUpdated Serbian translations for the bfd, gold, ld...
2022-02-15 H.J. Lux86: Add has_sib to struct instr_info
2022-02-14 Sergei Trofimovichmicroblaze: fix fsqrt collicion to build on glibc-2.35
2022-01-24 Nick CliftonUpdate Bulgarian, French, Romaniam and Ukranian transla...
2022-01-23 H.J. LuRegenerate Makefile.in files with automake 1.15.1
2022-01-23 H.J. LuRegenerate configure files with autoconf 2.69
2022-01-22 Nick CliftonChange version number to 2.38.50 and regenerate files
2022-01-22 Nick CliftonAdd markers for 2.38 branch
2022-01-21 Mike Frysingerdrop old unused stamp-h.in file
2022-01-17 Nick CliftonUpdate the config.guess and config.sub files from the...
2022-01-17 Jan Beulichx86: adjust struct instr_info field types
2022-01-17 Jan Beulichx86: drop index16 field
2022-01-17 Jan Beulichx86: drop most Intel syntax register name arrays
2022-01-17 Jan Beulichx86: fold variables in memory operand index handling
2022-01-17 Jan Beulichx86: constify disassembler static data
2022-01-14 Jan Beulichx86: drop ymmxmm_mode
2022-01-14 Jan Beulichx86: share yet more VEX table entries with EVEX decoding
2022-01-14 Jan Beulichx86: consistently use scalar_mode for AVX512-FP16 scala...
2022-01-14 Jan Beulichx86: record further wrong uses of EVEX.b
2022-01-14 Jan Beulichx86: reduce AVX512 FP set of insns decoded through...
2022-01-14 Jan Beulichx86: reduce AVX512-FP16 set of insns decoded through...
2022-01-06 Richard Sandifordaarch64: Add support for new SME instructions
2022-01-06 Jan Beulichx86: drop NoAVX insn attribute
2022-01-06 Jan Beulichx86: drop NoAVX from POPCNT
2022-01-06 Jan Beulichx86: drop some "comm" template parameters
2022-01-06 Jan Beulichx86: templatize FMA insn templates
2022-01-05 Vladimir Mezentsevopcodes: Make i386-dis.c thread-safe
2022-01-02 Alan ModraUpdate year range in copyright notice of binutils files
2022-01-01 Mike Frysingerunify 64-bit bfd checks
2021-12-24 Vineet GuptaRISC-V: Hypervisor ext: support Privileged Spec 1.12
2021-12-18 Vladimir Mezentsevx86: Terminate mnemonicendp in swap_operand()
2021-12-16 Nelson ChuRISC-V: Support svinval extension with frozen version...
2021-12-03 Richard Sandifordaarch64: Fix uninitialised memory
2021-12-03 Alan ModraRevert "Re: Don't compile some opcodes files when bfd...
2021-12-02 Richard Sandifordaarch64: Add BC instruction
2021-12-02 Richard Sandifordaarch64: Enforce P/M/E order for MOPS instructions
2021-12-02 Richard Sandifordaarch64: Add support for +mops
2021-12-02 Richard Sandifordaarch64: Add Armv8.8-A system registers
2021-12-02 Richard Sandifordaarch64: Add id_aa64isar2_el1
2021-12-02 Richard Sandifordaarch64: Tweak insn sequence code
2021-12-02 Richard Sandifordaarch64: Add maximum immediate value to aarch64_sys_reg
2021-12-02 Marcus NilssonAllow the --visualize-jumps feature to work with the...
2021-11-30 Richard Sandifordaarch64: Add missing system registers [PR27145]
2021-11-30 Richard Sandifordaarch64: Make LOR registers conditional on +lor
2021-11-30 Richard Sandifordaarch64: Remove ZIDR_EL1
2021-11-30 Richard Sandifordaarch64: Allow writes to MFAR_EL3
2021-11-30 Richard Sandifordaarch64: Mark PMSIDR_EL1 as read-only
2021-11-30 Richard Sandifordaarch64: Remove duplicate system register entries
2021-11-30 Nelson ChuRISC-V: The vtype immediate with more than the defined...
2021-11-30 Nelson ChuRISC-V: Dump vset[i]vli immediate as numbers once vsew...
2021-11-30 Mike Frysingeropcodes: enable silent build rules
2021-11-26 Andrew Burgessopcodes/riscv: add disassembler options support to...
2021-11-25 Nick CliftonFix building the AArch64 assembler and disassembler...
2021-11-25 Nick CliftonUpdated French translation for the opcodes directory.
2021-11-23 Alan ModraUpdate bug reporting address
2021-11-18 Alan ModraRe: Don't compile some opcodes files when bfd is 32...
2021-11-18 jiaweiRISC-V: Add instructions and operand set for z[fdq]inx
2021-11-17 Przemyslaw Wirkusaarch64: [SME] SVE2 instructions added to support SME
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add new SME system registers
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add SME mode selection and state access...
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add LD1x, ST1x, LDR and STR instructions
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add ZERO instruction
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add MOV and MOVA instructions
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add SME instructions
2021-11-17 Przemyslaw Wirkusaarch64: [SME] Add +sme option to -march
2021-11-17 Nelson ChuRISC-V: Support rvv extension with released version...
2021-11-16 jiaweiRISC-V: Scalar crypto instructions and operand set.
2021-11-12 Alan ModraDon't compile some opcodes files when bfd is 32-bit...
2021-11-11 Nelson ChuRISC-V: Dump objects according to the elf architecture...
2021-11-05 Alan ModraMissing va_end in aarch64-dis.c
2021-11-03 Mike Frysingeropcodes: d10v: simplify header includes
2021-11-01 Przemyslaw Wirkusarm: add armv9-a architecture to -march
2021-10-27 Alan Modraubsan: arm: undefined shift
2021-10-27 Nelson ChuRISC-V: Tidy riscv assembler and disassembler.
2021-10-27 Maciej W. Rozyckiopcodes: Fix RPATH not being set for dynamic libbfd...
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