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https://bugs.libre-soc.org/show_bug.cgi?id=985
[libreriscv.git]
/
openpower
/
sv
/
biginteger
/
divmnu64.c
2022-09-29
Jacob Lifshay
rename madded->maddedu for consistency with PowerISA...
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2022-04-27
Jacob Lifshay
fix UB
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2022-04-27
Jacob Lifshay
clean up code
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2022-04-27
Jacob Lifshay
format code
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2022-04-26
Luke Kenneth Casso...
start splitting out bigops
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2022-04-26
Jacob Lifshay
switch to using divrem_64_by_32 which follows semantics...
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2022-04-26
Jacob Lifshay
fix UB caused by lkcl in 1afca349cc91beebe7fd04260e0f9e...
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2022-04-26
Jacob Lifshay
format code
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2022-04-25
Luke Kenneth Casso...
https://bugs.libre-soc.org/show_bug.cgi?id=817#c31
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2022-04-25
Luke Kenneth Casso...
use shift-and-or rather than mul-and-add in
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2022-04-24
Luke Kenneth Casso...
use div/rem rather than re-calculate modulo from multiply
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2022-04-22
Jacob Lifshay
format code
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2022-04-22
Luke Kenneth Casso...
clarify estimate through explicit variable containing
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2022-04-22
Jacob Lifshay
check for expected divmnu failures
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2022-04-22
Jacob Lifshay
convert divmnu64.c tests to be easier to understand
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2022-04-22
Jacob Lifshay
add sv.madded sv.subfe to divmnu64.c
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2022-04-22
Jacob Lifshay
format with clang-format-13
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2022-04-22
Jacob Lifshay
add stuff for clang-format
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2022-04-19
Luke Kenneth Casso...
move c code to biginteger
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