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Verific build fixes
[yosys.git]
/
passes
/
abc
/
blifparse.cc
2015-05-13
Clifford Wolf
Added .barbuf support to abc BLIF parser
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-12-29
Clifford Wolf
Less verbose ABC output
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-15
Clifford Wolf
Renamed $lut ports to follow A-Y naming scheme
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2014-08-14
Clifford Wolf
Added module->ports
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-31
Clifford Wolf
Added module->design and cell->module, wire->module...
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-23
Clifford Wolf
Removed RTLIL::SigSpec::optimize()
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2014-03-11
Siesh1oo
Rebase to cliffordwolf repo HEAD finished.
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2014-03-11
Clifford Wolf
Fixed memory corruption in passes/abc/blifparse.cc
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2013-12-31
Clifford Wolf
Fixed use of limited length buffer in ABC blif parser
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2013-12-31
Clifford Wolf
Added abc -dff and -clk support
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2013-12-31
Clifford Wolf
Always use BLIF as ABC output format
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2013-11-19
Clifford Wolf
Renamed temp module generated by "abc" pass from "logic...
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2013-11-13
Clifford Wolf
Fixed abc pass blif parser for constant bits
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2013-07-23
Clifford Wolf
Added $lut cells and abc lut mapping support
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