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Merge pull request #1085 from YosysHQ/eddie/shregmap_improve
[yosys.git]
/
passes
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cmds
/
add.cc
2019-06-13
Serge Bazanski
Merge pull request #829 from abdelrahmanhosny/master
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2019-04-30
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-04-30
Benedikt Tutzer
Merge branch 'master' of https://github.com/YosysHQ...
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2019-04-22
Clifford Wolf
Merge pull request #905 from christian-krieg/feature...
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2019-04-22
Clifford Wolf
Merge pull request #941 from Wren6991/sim_lib_io_clke
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2019-04-22
Clifford Wolf
Merge branch 'master' of https://github.com/dh73/yosys_...
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2019-04-22
Clifford Wolf
Merge pull request #911 from mmicko/gowin-nobram
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2019-04-22
Clifford Wolf
Merge pull request #909 from zachjs/master
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2019-04-22
Clifford Wolf
Merge pull request #944 from YosysHQ/clifford/pmux2shiftx
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2019-04-21
Eddie Hung
Merge branch 'master' into map_cells_before_map_luts
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/clifford/pmux2shif...
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2019-04-21
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-20
Clifford Wolf
Merge pull request #943 from YosysHQ/clifford/whitebox
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2019-04-18
Clifford Wolf
Add "whitebox" attribute, add "read_verilog -wb"
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2013-11-22
Clifford Wolf
Renamed "placeholder" to "blackbox"
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2013-11-21
Clifford Wolf
Fixed a bug in "add -global_input"
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2013-11-20
Clifford Wolf
Added "add" command (only wires for now)
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