git.libre-soc.org Git - yosys.git/history

2014-07-27	Clifford Wolf	Refactoring: Renamed RTLIL::Design::modules to modules_	blob \| commitdiff \| raw
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::cells to cells_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::wires to wires_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed a lot of code to the new RTLIL::Wire constructors	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added RTLIL::Cell::has(portname)	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Merge automatic and manual code changes for new cell...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Manual fixes for new cell connections API	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed users of cell->connections_ to the new API...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Renamed RTLIL::{Module,Cell}::connections to connections_	blob \| commitdiff \| raw \| diff to current
2013-11-22	Clifford Wolf	Renamed "placeholder" to "blackbox"	blob \| commitdiff \| raw \| diff to current
2013-11-21	Clifford Wolf	Fixed a bug in "add -global_input"	blob \| commitdiff \| raw \| diff to current
2013-11-20	Clifford Wolf	Added "add" command (only wires for now)	blob \| commitdiff \| raw \| diff to current