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Merge pull request #1004 from YosysHQ/clifford/fix1002
[yosys.git]
/
passes
/
cmds
/
design.cc
2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2017-07-03
Clifford Wolf
Merge pull request #352 from rqou/master
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2017-06-30
Clifford Wolf
Add "design -import"
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2016-11-30
Clifford Wolf
Added "design -reset-vlog"
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2015-08-14
Clifford Wolf
Spell check (by Larry Doolittle)
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-02
Clifford Wolf
No implicit conversion from IdString to anything else
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2014-08-01
Clifford Wolf
Preparations for RTLIL::IdString redesign: cleanup...
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2014-07-31
Clifford Wolf
Added module->design and cell->module, wire->module...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-02-20
Clifford Wolf
Added "design -push" and "design -pop"
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2014-02-07
Clifford Wolf
Fixed use of "cmd_error" in passes/cmds/design.cc
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2014-02-06
Clifford Wolf
Added design -stash/-copy-from/-copy-to
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2013-07-27
Clifford Wolf
Added "design" command (-reset, -save, -load)
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