Fix "tee" handling of log_streams
[yosys.git] / passes / cmds / design.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2017-07-03 Clifford WolfMerge pull request #352 from rqou/master
2017-06-30 Clifford WolfAdd "design -import"
2016-11-30 Clifford WolfAdded "design -reset-vlog"
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2015-08-14 Clifford WolfSpell check (by Larry Doolittle)
2015-07-02 Clifford WolfFixed trailing whitespaces
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-02 Clifford WolfNo implicit conversion from IdString to anything else
2014-08-01 Clifford WolfPreparations for RTLIL::IdString redesign: cleanup...
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-31 Clifford WolfMoved some stuff to kernel/yosys.{h,cc}, using Yosys...
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-02-20 Clifford WolfAdded "design -push" and "design -pop"
2014-02-07 Clifford WolfFixed use of "cmd_error" in passes/cmds/design.cc
2014-02-06 Clifford WolfAdded design -stash/-copy-from/-copy-to
2013-07-27 Clifford WolfAdded "design" command (-reset, -save, -load)