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Merge remote-tracking branch 'origin/eddie/shregmap_improve' into xc7mux
[yosys.git]
/
passes
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cmds
/
rename.cc
2019-04-08
Eddie Hung
Merge branch 'master' into xaig
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2019-04-03
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7srl
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2019-04-02
Eddie Hung
Merge pull request #895 from YosysHQ/pmux2shiftx
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2019-04-01
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-03-28
Clifford Wolf
Merge pull request #903 from YosysHQ/bram_reset_transp
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2019-03-27
Clifford Wolf
Add "rename -output"
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2019-03-27
Clifford Wolf
Improve "rename" help message
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2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-01-07
Clifford Wolf
Merge pull request #782 from whitequark/flowmap_dfs
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2019-01-06
Clifford Wolf
Merge pull request #780 from phire/rename_from_wire
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2019-01-06
Scott Mansell
Rename cells based on the wires they drive.
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2018-12-18
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2018-12-16
Clifford Wolf
Merge pull request #736 from whitequark/select_assert_list
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2018-12-16
Clifford Wolf
Merge pull request #704 from webhat/feature/fix-awk
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2018-12-16
Clifford Wolf
Merge pull request #738 from smunaut/issue_737
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2018-12-16
Clifford Wolf
Merge pull request #735 from daveshah1/trifixes
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2018-12-16
Clifford Wolf
Merge pull request #724 from whitequark/equiv_opt
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2018-12-16
Clifford Wolf
Merge pull request #734 from grahamedgecombe/fix-shuffl...
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2018-12-16
Clifford Wolf
Merge pull request #730 from smunaut/ffssr_dont_touch
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2018-12-16
Clifford Wolf
Merge pull request #729 from whitequark/write_verilog_i...
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2018-12-16
Clifford Wolf
Merge pull request #725 from olofk/ram4k-init
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2018-12-16
Clifford Wolf
Merge pull request #714 from daveshah1/abc_preserve_naming
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2018-12-16
Clifford Wolf
Merge pull request #723 from whitequark/synth_ice40_map...
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2018-12-16
Clifford Wolf
Merge pull request #722 from whitequark/rename_src
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2018-12-05
whitequark
rename: add -src, for inferring names from source locat...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-06-29
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-06-29
Clifford Wolf
Added design->rename(module, new_name)
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2015-06-17
Clifford Wolf
Added "rename -top new_name"
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-08
Clifford Wolf
Fixed iterator invalidation bug in "rename" command
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2014-12-26
Clifford Wolf
Added Yosys::{dict,nodict,vector} container types
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2014-11-08
Clifford Wolf
Added missing fixup_ports() calls to "rename" command
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-26
Clifford Wolf
Implemented "rename -enumerate -pattern"
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Changed more code to the new RTLIL::Wire constructors
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-02
Clifford Wolf
Added "rename -hide" command
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2013-08-07
Clifford Wolf
Improved handling of private names in opt_clean and...
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2013-06-20
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-06-19
Clifford Wolf
Added renaming of wires and cells to "rename" command
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2013-06-10
Clifford Wolf
Added "rename" command
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