ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
[yosys.git] / passes / cmds / rename.cc
2019-06-13 Serge BazanskiMerge pull request #829 from abdelrahmanhosny/master
2019-04-08 Eddie HungMerge branch 'master' into xaig
2019-04-03 Eddie HungMerge remote-tracking branch 'origin/master' into xc7srl
2019-04-02 Eddie HungMerge pull request #895 from YosysHQ/pmux2shiftx
2019-04-01 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu...
2019-03-28 Clifford WolfMerge pull request #903 from YosysHQ/bram_reset_transp
2019-03-27 Clifford WolfAdd "rename -output"
2019-03-27 Clifford WolfImprove "rename" help message
2019-02-11 Jim LawsonMerge remote-tracking branch 'upstream/master'
2019-01-07 Clifford WolfMerge pull request #782 from whitequark/flowmap_dfs
2019-01-06 Clifford WolfMerge pull request #780 from phire/rename_from_wire
2019-01-06 Scott MansellRename cells based on the wires they drive.
2018-12-18 Jim LawsonMerge remote-tracking branch 'upstream/master'
2018-12-16 Clifford WolfMerge pull request #736 from whitequark/select_assert_list
2018-12-16 Clifford WolfMerge pull request #704 from webhat/feature/fix-awk
2018-12-16 Clifford WolfMerge pull request #738 from smunaut/issue_737
2018-12-16 Clifford WolfMerge pull request #735 from daveshah1/trifixes
2018-12-16 Clifford WolfMerge pull request #724 from whitequark/equiv_opt
2018-12-16 Clifford WolfMerge pull request #734 from grahamedgecombe/fix-shuffl...
2018-12-16 Clifford WolfMerge pull request #730 from smunaut/ffssr_dont_touch
2018-12-16 Clifford WolfMerge pull request #729 from whitequark/write_verilog_i...
2018-12-16 Clifford WolfMerge pull request #725 from olofk/ram4k-init
2018-12-16 Clifford WolfMerge pull request #714 from daveshah1/abc_preserve_naming
2018-12-16 Clifford WolfMerge pull request #723 from whitequark/synth_ice40_map...
2018-12-16 Clifford WolfMerge pull request #722 from whitequark/rename_src
2018-12-05 whitequarkrename: add -src, for inferring names from source locat...
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in...
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com...
2015-07-02 Clifford WolfFixed trailing whitespaces
2015-06-29 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2015-06-29 Clifford WolfAdded design->rename(module, new_name)
2015-06-17 Clifford WolfAdded "rename -top new_name"
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-02-08 Clifford WolfFixed iterator invalidation bug in "rename" command
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types
2014-11-08 Clifford WolfAdded missing fixup_ports() calls to "rename" command
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-08-26 Clifford WolfImplemented "rename -enumerate -pattern"
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-01-02 Clifford WolfAdded "rename -hide" command
2013-08-07 Clifford WolfImproved handling of private names in opt_clean and...
2013-06-20 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-06-19 Clifford WolfAdded renaming of wires and cells to "rename" command
2013-06-10 Clifford WolfAdded "rename" command