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Fixed trailing whitespaces
[yosys.git] / passes / cmds / rename.cc
2015-07-02 Clifford WolfFixed trailing whitespaces blob | commitdiff | raw
2015-06-29 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2015-06-29 Clifford WolfAdded design->rename(module, new_name) blob | commitdiff | raw | diff to current
2015-06-17 Clifford WolfAdded "rename -top new_name" blob | commitdiff | raw | diff to current
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2015-02-08 Clifford WolfFixed iterator invalidation bug in "rename" command blob | commitdiff | raw | diff to current
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types blob | commitdiff | raw | diff to current
2014-11-08 Clifford WolfAdded missing fixup_ports() calls to "rename" command blob | commitdiff | raw | diff to current
2014-09-27 Clifford Wolfnamespace Yosys blob | commitdiff | raw | diff to current
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-08-26 Clifford WolfImplemented "rename -enumerate -pattern" blob | commitdiff | raw | diff to current
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_ blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfChanged more code to the new RTLIL::Wire constructors blob | commitdiff | raw | diff to current
2014-01-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-01-02 Clifford WolfAdded "rename -hide" command blob | commitdiff | raw | diff to current
2013-08-07 Clifford WolfImproved handling of private names in opt_clean and... blob | commitdiff | raw | diff to current
2013-06-20 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2013-06-19 Clifford WolfAdded renaming of wires and cells to "rename" command blob | commitdiff | raw | diff to current
2013-06-10 Clifford WolfAdded "rename" command blob | commitdiff | raw | diff to current