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Fixed trailing whitespaces
[yosys.git]
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passes
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cmds
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rename.cc
2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-06-29
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2015-06-29
Clifford Wolf
Added design->rename(module, new_name)
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2015-06-17
Clifford Wolf
Added "rename -top new_name"
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2015-02-08
Clifford Wolf
Fixed iterator invalidation bug in "rename" command
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2014-12-26
Clifford Wolf
Added Yosys::{dict,nodict,vector} container types
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2014-11-08
Clifford Wolf
Added missing fixup_ports() calls to "rename" command
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-26
Clifford Wolf
Implemented "rename -enumerate -pattern"
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Changed more code to the new RTLIL::Wire constructors
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2014-01-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-01-02
Clifford Wolf
Added "rename -hide" command
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2013-08-07
Clifford Wolf
Improved handling of private names in opt_clean and...
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2013-06-20
Clifford Wolf
Merge branch 'master' of github.com:cliffordwolf/yosys
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2013-06-19
Clifford Wolf
Added renaming of wires and cells to "rename" command
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2013-06-10
Clifford Wolf
Added "rename" command
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