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ice40: Adapt the relut process passes to the new $lut <=> SB_LUT4 port map
[yosys.git] / passes / cmds / scatter.cc
2019-03-28 Benedikt TutzerMerge remote-tracking branch 'origin/master' into featu... blob | commitdiff | raw
2018-09-17 Udi FinkelsteinMerge branch 'master' into pr_reg_wire_error blob | commitdiff | raw
2018-08-22 Jim LawsonMerge pull request #1 from YosysHQ/master blob | commitdiff | raw
2018-08-18 Aman GoelMerge pull request #3 from YosysHQ/master blob | commitdiff | raw
2018-08-15 Clifford WolfMerge pull request #573 from cr1901/msys-64 blob | commitdiff | raw
2018-08-15 Clifford WolfMerge pull request #591 from hzeller/virtual-override blob | commitdiff | raw
2018-07-21 Henner ZellerConsistent use of 'override' for virtual methods in... blob | commitdiff | raw
2016-07-08 Clifford WolfMerge branch 'yosys-0.5-vtr' of https://github.com... blob | commitdiff | raw | diff to current
2015-07-02 Clifford WolfFixed trailing whitespaces blob | commitdiff | raw | diff to current
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-09-27 Clifford Wolfnamespace Yosys blob | commitdiff | raw | diff to current
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol... blob | commitdiff | raw | diff to current
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_ blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_ blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell... blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfManual fixes for new cell connections API blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API... blob | commitdiff | raw | diff to current
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_ blob | commitdiff | raw | diff to current
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every... blob | commitdiff | raw | diff to current
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun... blob | commitdiff | raw | diff to current
2013-08-21 Clifford WolfMerge pull request #10 from hansiglaser/master blob | commitdiff | raw | diff to current
2013-08-21 Clifford WolfSome minor documentation fixes blob | commitdiff | raw | diff to current
2013-06-12 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys blob | commitdiff | raw | diff to current
2013-06-12 Clifford WolfAdded "scatter" command blob | commitdiff | raw | diff to current