git.libre-soc.org Git - yosys.git/history

[yosys.git] / passes / fsm / fsm_detect.cc

2019-03-28	Benedikt Tutzer	Merge remote-tracking branch 'origin/master' into featu...	blob \| commitdiff \| raw
2019-02-11	Jim Lawson	Merge remote-tracking branch 'upstream/master'	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #770 from whitequark/opt_expr_cmp	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #755 from Icenowy/anlogic-dram-init	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #750 from Icenowy/anlogic-ff-init	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #773 from whitequark/opt_lut_elim_fixes	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #772 from whitequark/synth_lut	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #771 from whitequark/techmap_cmp2lut	blob \| commitdiff \| raw
2019-01-02	Clifford Wolf	Merge pull request #769 from whitequark/typos	blob \| commitdiff \| raw
2019-01-02	whitequark	Fix typographical and grammatical errors and inconsiste...	blob \| commitdiff \| raw
2018-09-17	Udi Finkelstein	Merge branch 'master' into pr_reg_wire_error	blob \| commitdiff \| raw \| diff to current
2018-08-22	Jim Lawson	Merge pull request #1 from YosysHQ/master	blob \| commitdiff \| raw \| diff to current
2018-08-18	Aman Goel	Merge pull request #3 from YosysHQ/master	blob \| commitdiff \| raw \| diff to current
2018-08-15	Clifford Wolf	Merge pull request #573 from cr1901/msys-64	blob \| commitdiff \| raw \| diff to current
2018-08-15	Clifford Wolf	Merge pull request #591 from hzeller/virtual-override	blob \| commitdiff \| raw \| diff to current
2018-07-21	Henner Zeller	Consistent use of 'override' for virtual methods in...	blob \| commitdiff \| raw \| diff to current
2017-04-12	Larry Doolittle	Squelch trailing whitespace	blob \| commitdiff \| raw \| diff to current
2016-07-09	Clifford Wolf	Further improved fsm_detect output, attempt to detect...	blob \| commitdiff \| raw \| diff to current
2016-07-09	Clifford Wolf	Added printing of some warning messages to fsm_detect	blob \| commitdiff \| raw \| diff to current
2016-07-08	Clifford Wolf	Merge branch 'yosys-0.5-vtr' of https://github.com...	blob \| commitdiff \| raw \| diff to current
2016-04-23	Andrew Zonenberg	Merge https://github.com/cliffordwolf/yosys	blob \| commitdiff \| raw \| diff to current
2016-04-21	Clifford Wolf	Added "yosys -D" feature	blob \| commitdiff \| raw \| diff to current
2015-12-07	Clifford Wolf	Merge pull request #108 from cseed/master	blob \| commitdiff \| raw \| diff to current
2015-09-21	Clifford Wolf	Do not detect fsm state registers with init attribute	blob \| commitdiff \| raw \| diff to current
2015-09-18	Clifford Wolf	Added $logic_not handling to fsm_detect	blob \| commitdiff \| raw \| diff to current
2015-08-18	Clifford Wolf	Bugfix in fsm_detect for complex muxtrees	blob \| commitdiff \| raw \| diff to current
2015-07-02	Clifford Wolf	Fixed trailing whitespaces	blob \| commitdiff \| raw \| diff to current
2015-04-03	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-11-09	Clifford Wolf	Added log_warning() API	blob \| commitdiff \| raw \| diff to current
2014-09-27	Clifford Wolf	namespace Yosys	blob \| commitdiff \| raw \| diff to current
2014-09-22	Ahmed Irfan	Merge branch 'master' of https://github.com/cliffordwol...	blob \| commitdiff \| raw \| diff to current
2014-08-14	Clifford Wolf	RIP $safe_pmux	blob \| commitdiff \| raw \| diff to current
2014-08-02	Clifford Wolf	More cleanups related to RTLIL::IdString usage	blob \| commitdiff \| raw \| diff to current
2014-07-31	Clifford Wolf	Renamed port access function on RTLIL::Cell, added...	blob \| commitdiff \| raw \| diff to current
2014-07-27	Clifford Wolf	Refactoring: Renamed RTLIL::Design::modules to modules_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::cells to cells_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::wires to wires_	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Added RTLIL::Cell::has(portname)	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Merge automatic and manual code changes for new cell...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Changed users of cell->connections_ to the new API...	blob \| commitdiff \| raw \| diff to current
2014-07-26	Clifford Wolf	Renamed RTLIL::{Module,Cell}::connections to connections_	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: using the accessor functions every...	blob \| commitdiff \| raw \| diff to current
2014-07-22	Clifford Wolf	SigSpec refactoring: renamed chunks and width to __chun...	blob \| commitdiff \| raw \| diff to current
2013-12-06	Clifford Wolf	Fixes in fsm detect/extract for better detection of...	blob \| commitdiff \| raw \| diff to current
2013-10-29	Clifford Wolf	Added detection for endless recursion in fsm_detect...	blob \| commitdiff \| raw \| diff to current
2013-03-18	Clifford Wolf	Merge branch 'hansi'	blob \| commitdiff \| raw \| diff to current
2013-03-18	Johann Glaser	fixed typos	blob \| commitdiff \| raw \| diff to current
2013-03-01	Clifford Wolf	Added help messages for fsm_* passes	blob \| commitdiff \| raw \| diff to current
2013-01-05	Clifford Wolf	initial import	blob \| commitdiff \| raw \| diff to current

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