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More idstring sort_by_* helpers and fixed tpl ordering in techmap
[yosys.git]
/
passes
/
fsm
/
fsm_expand.cc
2014-08-15
Clifford Wolf
More idstring sort_by_* helpers and fixed tpl ordering...
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2014-08-14
Clifford Wolf
RIP $safe_pmux
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2013-08-09
Clifford Wolf
Some fixes to improve determinism
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2013-03-25
Clifford Wolf
Improved method for finding fsm_expand candidates
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2013-03-24
Clifford Wolf
Changed fsm_expand to merge multiplexers more aggressively
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2013-03-18
Clifford Wolf
Merge branch 'hansi'
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2013-03-18
Johann Glaser
fixed typos
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2013-03-01
Clifford Wolf
Added help messages for fsm_* passes
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2013-01-05
Clifford Wolf
initial import
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