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Revert "Merge pull request #1917 from YosysHQ/eddie/abc9_delay_check"
[yosys.git]
/
passes
/
fsm
/
fsm_extract.cc
2020-04-15
N. Engelhardt
Merge pull request #1830 from boqwxp/qbfsat
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2020-04-10
whitequark
Merge pull request #1603 from whitequark/ice40-ram_style
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2020-04-08
Sahand Kashani
Merge branch 'master' of github.com:YosysHQ/yosys into...
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2020-04-07
Claire Wolf
Merge pull request #1814 from YosysHQ/mmicko/pyosys_mak...
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2020-04-06
whitequark
Merge pull request #1859 from boqwxp/design_duplicate
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2020-04-03
Eddie Hung
Merge pull request #1648 from YosysHQ/eddie/cmp2lcu
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2020-04-02
Eddie Hung
Merge pull request #1853 from YosysHQ/eddie/fix_dynslice
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2020-04-02
Eddie Hung
Merge pull request #1767 from YosysHQ/eddie/idstrings
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2020-04-02
Eddie Hung
kernel: big fat patch to use more ID::*, otherwise...
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2020-04-02
Eddie Hung
kernel: use more ID::*
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2020-04-02
Eddie Hung
Merge pull request #1845 from YosysHQ/eddie/kernel_speedup
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2020-04-02
Claire Wolf
Merge pull request #1770 from YosysHQ/claire/btor_symbols
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2020-04-02
Claire Wolf
Merge pull request #1765 from YosysHQ/claire/btor_info
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2020-04-01
Eddie Hung
Merge pull request #1828 from YosysHQ/eddie/celltypes_s...
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2020-04-01
Eddie Hung
Merge pull request #1790 from YosysHQ/eddie/opt_expr_xor
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2020-04-01
Eddie Hung
Merge pull request #1789 from YosysHQ/eddie/opt_expr_alu
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2020-04-01
Claire Wolf
Merge pull request #1848 from YosysHQ/eddie/fix_dynslice
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2020-03-31
Eddie Hung
Merge pull request #1761 from YosysHQ/eddie/opt_merge_s...
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2020-03-30
Eddie Hung
Merge pull request #1783 from boqwxp/astcc_cleanup
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2020-03-30
Eddie Hung
Merge pull request #1786 from boqwxp/hierarchycc_cleanup
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2020-03-27
Claire Wolf
Merge pull request #1607 from whitequark/simplify-simpl...
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2020-03-23
N. Engelhardt
Merge pull request #1763 from boqwxp/issue1762
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2020-03-23
N. Engelhardt
Merge pull request #1785 from boqwxp/mitercc_cleanup
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2020-03-19
Eddie Hung
Merge pull request #1788 from YosysHQ/eddie/fix_ndebug
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2020-03-19
Marcin KoĆcielnicki
fsm_extract: Initialize celltypes with full design.
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2020-01-29
Claire Wolf
Merge branch 'vector_fix' of https://github.com/Kmanfi...
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2019-09-27
Aman Goel
Merge pull request #7 from YosysHQ/master
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2019-08-26
Clifford Wolf
Merge tag 'yosys-0.9'
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2019-08-25
Clifford Wolf
Merge pull request #1112 from acw1251/pyosys_sigsig_issue
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2019-08-22
Clifford Wolf
Merge pull request #1281 from mmicko/efinix
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2019-08-20
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-16
Eddie Hung
Merge branch 'eddie/abc9_refactor' into xaig_dff
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2019-08-16
Eddie Hung
Merge pull request #1250 from bwidawsk/master
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2019-08-16
Eddie Hung
Merge https://github.com/bogdanvuk/yosys into bogdanvuk...
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2019-08-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into xc7dsp
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2019-08-12
Serge Bazanski
Merge pull request #1152 from 1138-4EB/feat-docker
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2019-08-12
Eddie Hung
Merge remote-tracking branch 'origin/master' into eddie...
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2019-08-10
Clifford Wolf
Merge pull request #1258 from YosysHQ/eddie/cleanup
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2019-08-07
Eddie Hung
RTLIL::S{0,1} -> State::S{0,1}
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2019-03-28
Benedikt Tutzer
Merge remote-tracking branch 'origin/master' into featu...
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2019-02-11
Jim Lawson
Merge remote-tracking branch 'upstream/master'
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2019-01-02
Clifford Wolf
Merge pull request #770 from whitequark/opt_expr_cmp
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2019-01-02
Clifford Wolf
Merge pull request #755 from Icenowy/anlogic-dram-init
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2019-01-02
Clifford Wolf
Merge pull request #750 from Icenowy/anlogic-ff-init
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2019-01-02
Clifford Wolf
Merge pull request #773 from whitequark/opt_lut_elim_fixes
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2019-01-02
Clifford Wolf
Merge pull request #772 from whitequark/synth_lut
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2019-01-02
Clifford Wolf
Merge pull request #771 from whitequark/techmap_cmp2lut
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2019-01-02
Clifford Wolf
Merge pull request #769 from whitequark/typos
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2019-01-02
whitequark
Fix typographical and grammatical errors and inconsiste...
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2018-09-17
Udi Finkelstein
Merge branch 'master' into pr_reg_wire_error
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2018-08-22
Jim Lawson
Merge pull request #1 from YosysHQ/master
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2018-08-18
Aman Goel
Merge pull request #3 from YosysHQ/master
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2018-08-15
Clifford Wolf
Merge pull request #573 from cr1901/msys-64
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2018-08-15
Clifford Wolf
Merge pull request #591 from hzeller/virtual-override
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2018-07-21
Henner Zeller
Consistent use of 'override' for virtual methods in...
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2016-07-13
Clifford Wolf
Merge pull request #191 from whitequark/json-module...
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2016-07-12
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-07-12
Clifford Wolf
Minor bugfix in FSM reset state detection
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2016-07-08
Clifford Wolf
Merge branch 'yosys-0.5-vtr' of https://github.com...
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2016-04-23
Andrew Zonenberg
Merge https://github.com/cliffordwolf/yosys
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2016-04-21
Clifford Wolf
Added "yosys -D" feature
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2015-07-03
Clifford Wolf
Bugfix in fsm_extract
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2015-07-02
Clifford Wolf
Fixed trailing whitespaces
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2015-04-29
Clifford Wolf
Added $eq/$neq -> $logic_not/$reduce_bool optimization
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2015-04-03
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-12-24
Clifford Wolf
Renamed extend() to extend_xx(), changed most users...
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2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-30
Clifford Wolf
Using $pmux info in fsm_extract to optimize transition...
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2014-08-30
Clifford Wolf
Improved handling of $pmux cells in fsm_extract
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2014-08-14
Clifford Wolf
RIP $safe_pmux
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2014-08-08
Clifford Wolf
Another fsm_extract bugfix
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2014-08-08
Clifford Wolf
Fixed fsm_extract for wreduced muxes
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2014-08-02
Clifford Wolf
More cleanups related to RTLIL::IdString usage
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-31
Clifford Wolf
Moved some stuff to kernel/yosys.{h,cc}, using Yosys...
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2014-07-28
Clifford Wolf
Using log_assert() instead of assert()
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::wires to wires_
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2014-07-26
Clifford Wolf
Changed a lot of code to the new RTLIL::Wire constructors
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2014-07-26
Clifford Wolf
Added RTLIL::Cell::has(portname)
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-25
Clifford Wolf
Use only module->addCell() and module->remove() to...
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2014-07-22
Clifford Wolf
SigSpec refactoring: cleanup of old SigSpec usage in...
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2014-07-22
Clifford Wolf
SigSpec refactoring: change RTLIL::SigSpec::chunks...
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2013-12-06
Clifford Wolf
Fixes in fsm detect/extract for better detection of...
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2013-12-04
Clifford Wolf
Replaced RTLIL::Const::str with generic decoder method
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2013-08-09
Clifford Wolf
Some fixes to improve determinism
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2013-08-08
Clifford Wolf
Sort ctrl signals in fsm_extract
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2013-06-05
Clifford Wolf
Renamed opt_rmunused to opt_clean
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2013-03-15
Clifford Wolf
Added [[CITE]] tags to abc and fsm_extract passes
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2013-03-01
Clifford Wolf
Added help messages for fsm_* passes
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2013-01-05
Clifford Wolf
Copy attributes from state signal to fsm cell
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