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Changed from "and" to "&&"
[yosys.git]
/
passes
/
fsm
/
fsm_opt.cc
2014-10-14
William Speirs
Changed from "and" to "&&"
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2014-10-10
Clifford Wolf
Renamed SIZE() to GetSize() because of name collision...
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2014-09-27
Clifford Wolf
namespace Yosys
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2014-09-22
Ahmed Irfan
Merge branch 'master' of https://github.com/cliffordwol...
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2014-08-09
Clifford Wolf
Some improvements in fsm_opt and fsm_map for FSM with...
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2014-07-31
Clifford Wolf
Renamed port access function on RTLIL::Cell, added...
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2014-07-27
Clifford Wolf
Refactoring: Renamed RTLIL::Design::modules to modules_
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2014-07-26
Clifford Wolf
Refactoring: Renamed RTLIL::Module::cells to cells_
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2014-07-26
Clifford Wolf
Merge automatic and manual code changes for new cell...
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2014-07-26
Clifford Wolf
Manual fixes for new cell connections API
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2014-07-26
Clifford Wolf
Changed users of cell->connections_ to the new API...
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2014-07-26
Clifford Wolf
Renamed RTLIL::{Module,Cell}::connections to connections_
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2014-07-22
Clifford Wolf
SigSpec refactoring: cleanup of old SigSpec usage in...
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2014-07-22
Clifford Wolf
fixed memory leak in fsm_opt
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2014-07-22
Clifford Wolf
SigSpec refactoring: using the accessor functions every...
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2014-07-22
Clifford Wolf
SigSpec refactoring: renamed chunks and width to __chun...
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2013-12-04
Clifford Wolf
Replaced RTLIL::Const::str with generic decoder method
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2013-06-05
Clifford Wolf
Renamed opt_rmunused to opt_clean
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2013-03-01
Clifford Wolf
Added help messages for fsm_* passes
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2013-01-05
Clifford Wolf
initial import
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