git.libre-soc.org Git - yosys.git/history

2014-07-27	Clifford Wolf	Refactoring: Renamed RTLIL::Design::modules to modules_	blob \| commitdiff \| raw
2014-07-26	Clifford Wolf	Refactoring: Renamed RTLIL::Module::cells to cells_	blob \| commitdiff \| raw \| diff to current
2014-03-11	Clifford Wolf	Merged a few fixes for non-posix systems from github...	blob \| commitdiff \| raw \| diff to current
2014-03-10	Siesh1oo	- passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode...	blob \| commitdiff \| raw \| diff to current
2013-12-04	Clifford Wolf	Replaced RTLIL::Const::str with generic decoder method	blob \| commitdiff \| raw \| diff to current
2013-05-24	Clifford Wolf	Improved FSM one-hot encoding, added binary encoding	blob \| commitdiff \| raw \| diff to current
2013-03-01	Clifford Wolf	Added help messages for fsm_* passes	blob \| commitdiff \| raw \| diff to current
2013-01-05	Clifford Wolf	initial import	blob \| commitdiff \| raw \| diff to current