2018-09-17 |
Udi Finkelstein | Merge branch 'master' into pr_reg_wire_error |
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2018-08-22 |
Jim Lawson | Merge pull request #1 from YosysHQ/master |
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2018-08-18 |
Aman Goel | Merge pull request #3 from YosysHQ/master |
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2018-08-15 |
Clifford Wolf | Merge pull request #573 from cr1901/msys-64 |
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2018-08-15 |
Clifford Wolf | Merge pull request #591 from hzeller/virtual-override |
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2018-07-21 |
Henner Zeller | Consistent use of 'override' for virtual methods in... |
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2017-08-21 |
Clifford Wolf | Remove some dead code from fsm_map |
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2017-04-12 |
Larry Doolittle | Squelch trailing whitespace |
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2017-02-09 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2017-01-31 |
Clifford Wolf | Merge branch 'opt_compare_pr' of https://github.com... |
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2017-01-26 |
Clifford Wolf | Be more conservative with merging large cells into... |
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2017-01-26 |
Clifford Wolf | Add warnings for quickly growing FSM table size in... |
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2016-11-02 |
Clifford Wolf | Added support for fsm_encoding="user" |
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2016-11-02 |
Clifford Wolf | Added "fsm_expand -full" |
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2016-10-25 |
Clifford Wolf | Bugfix in fsm_map for FSMs without reset state |
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2016-07-13 |
Clifford Wolf | Merge pull request #191 from whitequark/json-module... |
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2016-07-12 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2016-07-12 |
Clifford Wolf | Minor bugfix in FSM reset state detection |
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2016-07-09 |
Clifford Wolf | Further improved fsm_detect output, attempt to detect... |
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2016-07-09 |
Clifford Wolf | Added printing of some warning messages to fsm_detect |
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2016-07-08 |
Clifford Wolf | Merge branch 'yosys-0.5-vtr' of https://github.com... |
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2016-04-23 |
Andrew Zonenberg | Merge https://github.com/cliffordwolf/yosys |
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2016-04-21 |
Clifford Wolf | Added "yosys -D" feature |
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2016-02-13 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2016-02-13 |
Clifford Wolf | Added "int ceil_log2(int)" function |
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2015-12-07 |
Clifford Wolf | Merge pull request #108 from cseed/master |
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2015-10-25 |
Clifford Wolf | Import more std:: stuff into Yosys namespace |
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2015-10-24 |
Clifford Wolf | renamed SigSpec::to_single_sigbit() to SigSpec::as_bit... |
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2015-09-21 |
Clifford Wolf | Do not detect fsm state registers with init attribute |
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2015-09-18 |
Clifford Wolf | Added $logic_not handling to fsm_detect |
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2015-08-18 |
Clifford Wolf | Bugfix in fsm_detect for complex muxtrees |
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2015-08-14 |
Clifford Wolf | Spell check (by Larry Doolittle) |
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2015-07-03 |
Clifford Wolf | Bugfix in fsm_extract |
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2015-07-02 |
Clifford Wolf | Fixed trailing whitespaces |
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2015-04-29 |
Clifford Wolf | Added $eq/$neq -> $logic_not/$reduce_bool optimization |
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2015-04-03 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2015-02-04 |
Clifford Wolf | Added onehot attribute |
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2015-01-30 |
Clifford Wolf | Added "fsm -encfile" |
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2014-12-26 |
Clifford Wolf | Added Yosys::{dict,nodict,vector} container types |
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2014-12-24 |
Clifford Wolf | Renamed extend() to extend_xx(), changed most users... |
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2014-11-09 |
Clifford Wolf | Added log_warning() API |
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2014-10-14 |
Clifford Wolf | Merge branch 'win32' |
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2014-10-14 |
William Speirs | Changed from "and" to "&&" |
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2014-10-11 |
Clifford Wolf | Do not the 'z' modifier in format string (another win32... |
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2014-10-10 |
Clifford Wolf | Renamed SIZE() to GetSize() because of name collision... |
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2014-09-27 |
Clifford Wolf | namespace Yosys |
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2014-09-22 |
Ahmed Irfan | Merge branch 'master' of https://github.com/cliffordwol... |
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2014-09-06 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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2014-09-06 |
Clifford Wolf | Merge pull request #38 from rubund/master |
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2014-09-06 |
Ruben Undheim | Corrected spelling mistakes found by lintian |
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2014-08-30 |
Clifford Wolf | Don't change existing binary FSM encoding if it is... |
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2014-08-30 |
Clifford Wolf | Using $pmux info in fsm_extract to optimize transition... |
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2014-08-30 |
Clifford Wolf | Improved handling of $pmux cells in fsm_extract |
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2014-08-16 |
Clifford Wolf | Added module->uniquify() |
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2014-08-15 |
Clifford Wolf | More idstring sort_by_* helpers and fixed tpl ordering... |
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2014-08-14 |
Clifford Wolf | RIP $safe_pmux |
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2014-08-14 |
Clifford Wolf | Some improvements in FSM mapping and recoding |
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2014-08-10 |
Clifford Wolf | Fixed FSM mapping for multiple reset-like signals |
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2014-08-09 |
Clifford Wolf | Some improvements in fsm_opt and fsm_map for FSM with... |
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2014-08-08 |
Clifford Wolf | Another fsm_extract bugfix |
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2014-08-08 |
Clifford Wolf | Fixed "fsm -export" |
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2014-08-08 |
Clifford Wolf | Fixed fsm_extract for wreduced muxes |
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2014-08-02 |
Clifford Wolf | No implicit conversion from IdString to anything else |
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2014-08-02 |
Clifford Wolf | More cleanups related to RTLIL::IdString usage |
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2014-07-31 |
Clifford Wolf | Renamed port access function on RTLIL::Cell, added... |
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2014-07-31 |
Clifford Wolf | Moved some stuff to kernel/yosys.{h,cc}, using Yosys... |
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2014-07-28 |
Clifford Wolf | Using log_assert() instead of assert() |
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2014-07-27 |
Clifford Wolf | Added log_cmd_error_expection |
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2014-07-27 |
Clifford Wolf | Refactoring: Renamed RTLIL::Design::modules to modules_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::cells to cells_ |
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2014-07-26 |
Clifford Wolf | Refactoring: Renamed RTLIL::Module::wires to wires_ |
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2014-07-26 |
Clifford Wolf | Changed a lot of code to the new RTLIL::Wire constructors |
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2014-07-26 |
Clifford Wolf | Added RTLIL::Cell::has(portname) |
tree | commitdiff |
2014-07-26 |
Clifford Wolf | Merge automatic and manual code changes for new cell... |
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2014-07-26 |
Clifford Wolf | Manual fixes for new cell connections API |
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2014-07-26 |
Clifford Wolf | Changed users of cell->connections_ to the new API... |
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2014-07-26 |
Clifford Wolf | Renamed RTLIL::{Module,Cell}::connections to connections_ |
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2014-07-25 |
Clifford Wolf | Use only module->addCell() and module->remove() to... |
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2014-07-23 |
Clifford Wolf | Various small fixes (from gcc compiler warnings) |
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2014-07-23 |
Clifford Wolf | Removed RTLIL::SigSpec::optimize() |
tree | commitdiff |
2014-07-23 |
Clifford Wolf | Merge branch: Refactoring {SigSpec|SigChunk}(RTLIL... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
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2014-07-23 |
Clifford Wolf | Refactoring {SigSpec|SigChunk}(RTLIL::Wire *wire, ... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: cleanup of old SigSpec usage in... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | fixed memory leak in fsm_opt |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: change RTLIL::SigSpec::chunks... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: using the accessor functions every... |
tree | commitdiff |
2014-07-22 |
Clifford Wolf | SigSpec refactoring: renamed chunks and width to __chun... |
tree | commitdiff |
2014-03-11 |
Clifford Wolf | Merged a few fixes for non-posix systems from github... |
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2014-03-10 |
Siesh1oo | - passes/techmap/dfflibmap.cc, passes/fsm/fsm_recode... |
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2013-12-06 |
Clifford Wolf | Fixes in fsm detect/extract for better detection of... |
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2013-12-04 |
Clifford Wolf | Replaced RTLIL::Const::str with generic decoder method |
tree | commitdiff |
2013-10-29 |
Clifford Wolf | Added detection for endless recursion in fsm_detect... |
tree | commitdiff |
2013-08-09 |
Clifford Wolf | Some fixes to improve determinism |
tree | commitdiff |
2013-08-08 |
Clifford Wolf | Sort ctrl signals in fsm_extract |
tree | commitdiff |
2013-06-05 |
Clifford Wolf | Renamed opt_rmunused to opt_clean |
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2013-05-24 |
Clifford Wolf | Added -nodetect option to fsm pass |
tree | commitdiff |
2013-05-24 |
Clifford Wolf | Improved FSM one-hot encoding, added binary encoding |
tree | commitdiff |
2013-05-16 |
Clifford Wolf | Merge branch 'bugfix' |
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2013-04-07 |
Clifford Wolf | Merge branch 'master' of github.com:cliffordwolf/yosys |
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