Improved attributes API and handling of "src" attributes
[yosys.git] / passes / hierarchy /
2015-04-04 Clifford WolfAdded "dffinit", Support for initialized Xilinx DFF
2015-04-03 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2015-03-29 Clifford Wolfdocumentation improvements
2015-03-18 Clifford WolfAdded hierarchy -auto-top
2015-03-04 Clifford WolfFixed bug in "hierarchy" for parametric designs
2015-02-15 Clifford WolfCosmetic fixes in "hierarchy" for blackbox modules
2015-01-04 Clifford WolfFixed pattern matching in "hierarchy -generate"
2014-12-26 Clifford WolfAdded Yosys::{dict,nodict,vector} container types
2014-12-24 Clifford WolfFixed off-by-one bug in "hierarchy -check" for position...
2014-12-19 Clifford WolfChecking existence of ports in "hierarchy -check"
2014-11-27 Clifford WolfFixed bug in "hierarchy -top" with array of instances
2014-11-09 Clifford WolfAdded log_warning() API
2014-10-17 Clifford WolfVarious win32 / vs build fixes
2014-10-17 William SpeirsHeader changes so it will compile on VS
2014-10-11 Clifford WolfDo not the 'z' modifier in format string (another win32...
2014-10-10 Clifford WolfMoved patmatch() to yosys.cc
2014-10-10 Clifford WolfReplaced fnmatch() with patmatch()
2014-09-30 Clifford Wolfset "keep" on modules with $assert cells in "hierarchy"
2014-09-27 Clifford Wolfnamespace Yosys
2014-09-22 Ahmed IrfanMerge branch 'master' of https://github.com/cliffordwol...
2014-09-06 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2014-09-06 Clifford WolfMerge pull request #38 from rubund/master
2014-09-06 Ruben UndheimCorrected spelling mistakes found by lintian
2014-08-14 Clifford WolfAdded module->ports
2014-08-02 Clifford WolfMore bugfixes related to new RTLIL::IdString
2014-08-02 Clifford WolfMore cleanups related to RTLIL::IdString usage
2014-07-31 Clifford WolfRenamed port access function on RTLIL::Cell, added...
2014-07-31 Clifford WolfAdded module->design and cell->module, wire->module...
2014-07-29 Clifford WolfAllow "hierarchy -generate" for $__ cells
2014-07-28 Clifford WolfUsing log_assert() instead of assert()
2014-07-27 Clifford WolfRefactoring: Renamed RTLIL::Design::modules to modules_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::cells to cells_
2014-07-26 Clifford WolfRefactoring: Renamed RTLIL::Module::wires to wires_
2014-07-26 Clifford WolfChanged a lot of code to the new RTLIL::Wire constructors
2014-07-26 Clifford WolfMerge automatic and manual code changes for new cell...
2014-07-26 Clifford WolfManual fixes for new cell connections API
2014-07-26 Clifford WolfChanged users of cell->connections_ to the new API...
2014-07-26 Clifford WolfRenamed RTLIL::{Module,Cell}::connections to connections_
2014-07-25 Clifford WolfAdded copy-constructor-like module->addCell(name, other...
2014-07-25 Clifford WolfUse only module->addCell() and module->remove() to...
2014-07-23 Clifford WolfFixed all users of SigSpec::chunks_rw() and removed it
2014-07-22 Clifford WolfSigSpec refactoring: change RTLIL::SigSpec::chunks...
2014-07-22 Clifford WolfSigSpec refactoring: using the accessor functions every...
2014-07-22 Clifford WolfSigSpec refactoring: renamed chunks and width to __chun...
2014-07-20 Clifford WolfAdded call_on_selection() and call_on_module() API
2014-06-07 Clifford Wolffixed cell array handling of positional arguments
2014-06-07 Clifford WolfAdd support for cell arrays
2014-02-13 Clifford WolfImplemented read_verilog -defer
2014-02-08 Clifford WolfMoved some passes to other source directories
2014-02-04 Clifford WolfAdded hierarchy -purge_lib option
2014-01-15 Ahmed IrfanMerge branch 'master' of https://github.com/ahmedirfan1...
2014-01-15 Ahmed IrfanMerge pull request #2 from cliffordwolf/master
2014-01-14 Clifford WolfMerge pull request #20 from mschmoelzer/master
2014-01-14 Martin SchmölzerInclude unistd.h in passes/hierarchy/hierarchy.cc ...
2014-01-14 Clifford WolfAdded hierarchy -libdir option
2013-12-04 Clifford WolfReplaced signed_parameters API with CONST_FLAG_SIGNED
2013-11-24 Clifford WolfRemove auto_wire framework (smarter than the verilog...
2013-11-24 Clifford WolfImplemented correct handling of signed module parameters
2013-11-24 Clifford WolfAdded "top" attribute to mark top module in hierarchy
2013-11-22 Clifford WolfRenamed "placeholder" to "blackbox"
2013-11-03 Clifford WolfMerge branch 'master' of github.com:cliffordwolf/yosys
2013-11-03 Clifford WolfAdded resolution of positional arguments to hierarchy...
2013-10-24 Clifford WolfFixed handling of boolean attributes (passes)
2013-05-26 Clifford WolfImproved log messages generated by hierarchy pass
2013-05-16 Clifford WolfMerge branch 'bugfix'
2013-04-26 Clifford WolfFixed hierarchy pass for hierarchies of parametric...
2013-03-28 Clifford WolfImplemented proper handling of stub placeholder modules
2013-03-26 Clifford WolfCollect parameters in hierarchy -generate (and do nothi...
2013-03-25 Clifford WolfAdded hierarchy -generate command for generating skelet...
2013-03-03 Clifford WolfImplemented general handler for selection arguments
2013-02-28 Clifford WolfAdded online help for "show" and "hierarchy" commands
2013-01-05 Clifford Wolfinitial import